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AM3874 PLL setting

Michi Yama
Guru 10030 points
Other Parts Discussed in Thread: AM3874

Hi,

I have two questions for PLL of AM3874. Please see the below.

1. DPLLS(MPUPLL) : My customer would like to evaluate the DPLLS(MPUPLL) of AM3874. Are there some signals for the monitoring? If there are not any signals for the monitoring, how does my customer evaluate the DPLLS(MPUPLL)? Please let me know how to do the evaluation.

2. DDRPLL :  My customer uses 20MHz clock as DEVOSC. And customer measured DDR_CLK (400MHz). Customer said me it seems that DDR_CLK is not synchronus to 20MHz clock.  Then, they changed the ENSSC bit(bit 30) of DDRPLL_CLKCTRL register(offset=294h) to "1". But  they could not see any changes the relation between 20MHz and 400MHz.

Also they say the meaning of ENSSC bit  of DDRPLL_CLKCTRL register and SSCACK bit of DDRPLL_STATUS register is opposite. Please check it.

My customer does not have time for this issue. So quick reply is very helpful.

Best regards,

Michi 

  • 0
    TI__Guru**** 170625 points

    Hi Michi,

    Michi Yama said:
    1. DPLLS(MPUPLL) : My customer would like to evaluate the DPLLS(MPUPLL) of AM3874. Are there some signals for the monitoring? If there are not any signals for the monitoring, how does my customer evaluate the DPLLS(MPUPLL)? Please let me know how to do the evaluation.

    You can monitor the MPUPLL_STATUS register. If there will be an issue with the MPU DPLL, the MPUPLL_STATUS should give you the reason.

    Do you have any specific problem with the MPU DPLL? What is the frequency you need to output from the MPU DPLL?

    Michi Yama said:

    Also they say the meaning of ENSSC bit  of DDRPLL_CLKCTRL register and SSCACK bit of DDRPLL_STATUS register is opposite. Please check it.

    Yes, I also think so. We should have:

    DDRPLL_CLKCTRL[30] ENSSC  0x0: disable clock spreading  0x1: enable clock spreading. One other community member reported the same:

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/273394.aspx

    DDRPLL_STATUS[2] SSCACK  0x0: Spread-spectrum Clocking is disabled   0x1: Spread-spectrum Clocking is enabled

    I will report this to the TRM team.

    Best regards,
    Pavel