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Network On Chip and OCP

Lusheng zhang
Intellectual 440 points
Other Parts Discussed in Thread: SYSBIOS

DM8168 platform OCP CLK is 400MHz. Cortex A8 CPU CLK is 1GHz ;sysbios 6.33

 How many cycles will it take to read or write one 32bit word from  L3 or L4 space (uncache unbuffer)?

I donot know the efficiency of the interconnect bus.

  • 0
    TI__Expert 8780 points

    Lusheng,

    Continuous access from A8 to other targets in L3 or L4 or DDR are pipelined. For most ports which are 128-bit wide L3 offers an end-to-end throughput of 3.2 Gbps. Thus performance is not an issue in L3 for most or all target applications.

    However the latency for one 32-bit word access (cycles) can wary depending upon system load.

    Following should hold true

    - Latency from A8 to DDR is minimum because A8 doesn't go via L3 for DDR accesses.

    - Latency for L3 target access is much lesser than for L4 target accesses.

    Regards

    Rajat

  • 0 in reply to Rajat Sagar
    Intellectual 440 points

    Thanks. I still have questions.

    But When measure the cycles of  reading uncacheable space , I find that it costs so much time.

    Reading TIMER_COUNTER for 1000 times, it need 3500 timer ticks(timer clock is 27M,  37 us), Reading one timer register costs 130 us (3.5 timer ticks). 

     reading DMA controller register for 1000 times, it need 2400 timer ticks(timer clock is 27M,  37 us ) . Reading one dma controller register costs 89 us(2.4 timer ticks).

    reading one word OCMC1(uncache unbufffer) for 1000 times, it need 2400 timer ticks(timer clock is 27M,  37 us ) . Reading one word of OCMC1(uncache unbufffer)  costs 89 us(2.4 timer ticks).

    I think it is too slow to read uncacheable space.