Minimum requirements for enabling data-cache?

Graeme Smecher

Other Parts Discussed in Thread: AM3874

Hi,

I'm attempting to work around a hardware bug in my DDR3 interface. I have a 16-bit DDR3 chip (MT41J256M16) with the LDM/UDM traces swapped between the RAM and my AM3874. The symptoms are:

32-bit RAM reads and writes appear fine (e.g. u-boot "mtest" command);
8-bit RAM reads appear fine (e.g. u-boot "getenv_r" function);
8-bit RAM writes don't work (e.g. what u-boot does with the "getenv_r" call to retrieve the baud rate)

My question is: I should be able to work around this hardware bug (for now) by enabling data cache, which prevents all 8-bit accesses. What is the bare minimum required for this? Specifically, do I need to configure the MMU?

Naively, I'd expect that enabling L1 data cache as follows is sufficient:

Setting the C bit in the Control Register; and
Setting the L1 hardware "reset disable" bit in the Auxiliary Control Register

However, I see the u-boot code configures data cache only in conjunction with the MMU:

 91 static void cache_enable(uint32_t cache_bit)
 92 {
 93    uint32_t reg;
 94 
 95    /* The data cache is not active unless the mmu is enabled too */
 96    if ((cache_bit == CR_C) && !mmu_enabled())
 97       mmu_setup();
 98 
 99    reg = get_cr(); /* get control reg. */
100    cp_delay();
101    set_cr(reg | cache_bit);
102 }

Can someone please clarify this for me? If the MMU is a requirement for data-cache function, can you refer me to the appropriate section in AM3874 documentation or the Cortex-A8 TRM? I can see why this might be a requirement, but I should be able to confirm it in the documentation somewhere.

thanks,

Graeme

over 12 years ago

0 Graeme Smecher over 12 years ago

Intellectual 415 points

Hi all,

Answering my own question. Enabling dcache to avoid 8-bit writes (and thus working around swapped UDM/LDM lines) does work fine in u-boot. It should, in principle, work fine for Linux, although I haven't modified the kernel's boot code yet.

Getting it to work involved a couple of steps:

adding a new init function (just after interrupt_init) to enable the cache before any 8-bit writes occur. The first such write occurs in getenv_r, as part of the UART initialization
modifying the page_table initialization code so that the combination of the TEX, C, and B bits force a write-through, write-allocated cache
removing the l2_disable_wa() workaround in evm.c (which disables write-allocation to work around a starvation issue that's not relevant to me.)

With cache enabled, I can limp into a u-boot prompt. Once write-allocation is also enabled, I'm able to boot without any apparent bugs.

best,

Graeme

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Minimum requirements for enabling data-cache?