Hi,
I have a same ploblem.
I'm also using uPP(C6655) to receive data from FPGA with start signal. but, I can not receive the data correctly.
After the enable signal is inactive, uPP does not receive the data when enable signal become active again.
In order to receive the data successfully, It seems that it is necessary to reactivate start signal and enable signal.
So please tell me the role of start signal and correct timing graph.
Best regards,
Chi