Hello,
I'm trying to bring up an Omap4470 board that is working in ICS, but now being ported to JellyBean 4AJ.2.5. I'm having problem getting the display to show anything, so I'm posting here hoping someone can take a look to see if someone can help, especially with the vertical/horizontal porch settings. Here is the vendor spec for the panel:
Here's my board file settings for this panel. It is on dsi1:
struct omap_video_timings pinnacle_dispc_timings = {
.x_res = 480,
.y_res = 800,
.hfp = 64,
.hsw = 14,
.hbp = 12,
.vfp = 19,
.vsw = 20,
.vbp = 21,
};
static struct omap_dss_device pinnacle_lcd_device = {
.name = "lcd",
.driver_name = "d2l", // "com40h4m42uly",
.type = OMAP_DISPLAY_TYPE_DSI,
.data = &pinnacle_dsi_panel,
.phy.dsi = {
.clk_lane = 1,
.clk_pol = 0,
.data1_lane = 2,
.data1_pol = 0,
.data2_lane = 3,
.data2_pol = 0,
//.data3_lane = 4,
//.data3_pol = 0,
//.data4_lane = 5,
//.data4_pol = 0,
.module = 0,
.ext_te = false, // No TE for Ortus
.ext_te_gpio = -1, // No TE, so no GPIO for TE
},
.clocks = {
.dispc = {
.channel = {
.lck_div = 1,
.pck_div = 6, // orig = 2, Jorge = 4
.lcd_clk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
},
// .dispc_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
.dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK,
},
.dsi = {
.regn = 16, // mtp according to Jorge
.regm = 145, // 240, // 145, // orig - DSI_PLL_CONFIGURATION1: regm
.regm_dispc = 4, // DSI_PLL_CONFIGURATION1: M4_CLOCK_DIV?
.regm_dsi = 5, // DSI_PLL_CONFIGURATION1: M5_CLOCK_DIV?
.lp_clk_div = 8, // 14, // 8, // orig: 5. This gives 4.5Mhz baud rate in the low speed mode
.offset_ddr_clk = 0,
//.dsi_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
.dsi_fclk_src = OMAP_DSS_CLK_SRC_FCK,
},
},
.panel = {
.timings = {
.x_res = 480,
.y_res = 800,
.pixel_clock = 33140,
.hfp = 64,
.hsw = 14,
.hbp = 12,
.vfp = 19,
.vsw = 20,
.vbp = 21,
},
.acbi = 0,
.acb = 0,
.config = ( (OMAP_DSS_LCD_RF) | (OMAP_DSS_LCD_ONOFF) | (OMAP_DSS_LCD_IVS) | (OMAP_DSS_LCD_IHS) ),
.dsi_mode = OMAP_DSS_DSI_VIDEO_MODE,
.dsi_vm_data = {
.hsa = 8, // 0,
.hfp = 59, // 102, // 59, // 64, // 4,
.hbp = 9, // 6, // 14, // 12, // 3,
.vsa = 20, // 2,
.vfp = 19, // 147, // 19, // 6,
.vbp = 21, // 4,
.vp_de_pol = true,
.vp_vsync_pol = false, // mtp, old: true,
.vp_hsync_pol = false,
.vp_hsync_end = true, // old: false,
.vp_vsync_end = true, // old: false,
.blanking_mode = 0,
.hsa_blanking_mode = 1,
.hfp_blanking_mode = 1,
.hbp_blanking_mode = 1,
.ddr_clk_always_on = true,
.window_sync = 4,
}
},
.ctrl = {
.pixel_size = 24,
},
.reset_gpio = LCD_RESET_GPIO,
.channel = OMAP_DSS_CHANNEL_LCD,
.platform_enable = NULL,
.platform_disable = NULL,
.dispc_timings = &pinnacle_dispc_timings,
};
Here is what I get from the sysfs debug:
clk:
- DSS -
dpll4_ck 1536000000
DSS_FCK (DSS_FCLK) = 1536000000 / 9 = 170666666
- DISPC -
dispc fclk source = DSS_FCK (DSS_FCLK)
fck 170666666
- DISPC-CORE-CLK -
lck 170666666 lck div 1
- LCD1 -
lcd1_clk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
lck 87000000 lck div 1
pck 14500000 pck div 6
- LCD2 -
lcd2_clk source = DSS_FCK (DSS_FCLK)
lck 42666666 lck div 4
pck 42666666 pck div 1
- DSI1 PLL -
dsi pll source = dss_sys_clk
Fint 1200000 regn 16
CLKIN4DDR 348000000 regm 145
DSI_PLL_HSDIV_DISPC (PLL1_CLK1) 87000000 regm_dispc 4 (off)
DSI_PLL_HSDIV_DSI (PLL1_CLK2) 69600000 regm_dsi 5 (off)
- DSI1 -
dsi fclk source = DSS_FCK (DSS_FCLK)
DSI_FCLK 170666666
DDR_CLK 87000000
TxByteClkHS 21750000
LP_CLK 10666666
dispc:
DISPC_REVISION 00000041
DISPC_SYSCONFIG 00002015
DISPC_SYSSTATUS 00000001
DISPC_IRQSTATUS 000000a2
DISPC_IRQENABLE 0012d640
DISPC_CONTROL 00000309
DISPC_CONFIG 00024004
DISPC_CAPABLE 00000000
DISPC_LINE_STATUS 00000048
DISPC_LINE_NUMBER 00000000
DISPC_GLOBAL_ALPHA ffffffff
DISPC_CONTROL2 00000000
DISPC_CONFIG2 00000000
DISPC_DEFAULT_COLOR(LCD) 00000000
DISPC_TRANS_COLOR(LCD) 00000000
DISPC_SIZE_MGR(LCD) 031f01df
DISPC_DEFAULT_COLOR(LCD) 00000000
DISPC_TRANS_COLOR(LCD) 00000000
DISPC_TIMING_H(LCD) 00b03f0d
DISPC_TIMING_V(LCD) 01501313
DISPC_POL_FREQ(LCD) 00000000
DISPC_DIVISORo(LCD) 00010006
DISPC_SIZE_MGR(LCD) 031f01df
DISPC_DATA_CYCLE1(LCD) 00000000
DISPC_DATA_CYCLE2(LCD) 00000000
DISPC_DATA_CYCLE3(LCD) 00000000
DISPC_CPR_COEF_R(LCD) 00000000
DISPC_CPR_COEF_G(LCD) 00000000
DISPC_CPR_COEF_B(LCD) 00000000
DISPC_DEFAULT_COLOR(TV) 00000000
DISPC_TRANS_COLOR(TV) 00000000
DISPC_SIZE_MGR(TV) 00000000
DISPC_DEFAULT_COLOR(LCD2) 00000000
DISPC_TRANS_COLOR(LCD2) 00000000
DISPC_SIZE_MGR(LCD2) 00000000
DISPC_DEFAULT_COLOR(LCD2) 00000000
DISPC_TRANS_COLOR(LCD2) 00000000
DISPC_TIMING_H(LCD2) 00000000
DISPC_TIMING_V(LCD2) 00000000
DISPC_POL_FREQ(LCD2) 00000000
DISPC_DIVISORo(LCD2) 00040001
DISPC_SIZE_MGR(LCD2) 00000000
DISPC_DATA_CYCLE1(LCD2) 00000000
DISPC_DATA_CYCLE2(LCD2) 00000000
DISPC_DATA_CYCLE3(LCD2) 00000000
DISPC_CPR_COEF_R(LCD2) 00000000
DISPC_CPR_COEF_G(LCD2) 00000000
DISPC_CPR_COEF_B(LCD2) 00000000
DISPC_OVL_BA0(GFX) 97c00000
DISPC_OVL_BA1(GFX) 97c00000
DISPC_OVL_POSITION(GFX) 00000000
DISPC_OVL_SIZE(GFX) 031f01df
DISPC_OVL_ATTRIBUTES(GFX) 02004099
DISPC_OVL_FIFO_THRESHOLD(GFX) 1cff0280
DISPC_OVL_FIFO_SIZE_STATUS(GFX) 00000500
DISPC_OVL_ROW_INC(GFX) 00000001
DISPC_OVL_PIXEL_INC(GFX) 00000001
DISPC_OVL_PRELOAD(GFX) 00000fff
DISPC_OVL_WINDOW_SKIP(GFX) 00000000
DISPC_OVL_TABLE_BA(GFX) 00000000
DISPC_OVL_BA0(VID1) 00000000
DISPC_OVL_BA1(VID1) 00000000
DISPC_OVL_POSITION(VID1) 00000000
DISPC_OVL_SIZE(VID1) 00000000
DISPC_OVL_ATTRIBUTES(VID1) 02008400
DISPC_OVL_FIFO_THRESHOLD(VID1) 00000000
DISPC_OVL_FIFO_SIZE_STATUS(VID1) 00000800
DISPC_OVL_ROW_INC(VID1) 00000001
DISPC_OVL_PIXEL_INC(VID1) 00000001
DISPC_OVL_PRELOAD(VID1) 00000000
DISPC_OVL_FIR(VID1) 04000400
DISPC_OVL_PICTURE_SIZE(VID1) 00000000
DISPC_OVL_ACCU0(VID1) 00000000
DISPC_OVL_ACCU1(VID1) 00000000
DISPC_OVL_BA0_UV(VID1) 00000000
DISPC_OVL_BA1_UV(VID1) 00000000
DISPC_OVL_FIR2(VID1) 04000400
DISPC_OVL_ACCU2_0(VID1) 00000000
DISPC_OVL_ACCU2_1(VID1) 00000000
DISPC_OVL_ATTRIBUTES2(VID1) 00000000
DISPC_OVL_PRELOAD(VID1) 00000000
DISPC_OVL_BA0(VID2) 00000000
DISPC_OVL_BA1(VID2) 00000000
DISPC_OVL_POSITION(VID2) 00000000
DISPC_OVL_SIZE(VID2) 00000000
DISPC_OVL_ATTRIBUTES(VID2) 02008400
DISPC_OVL_FIFO_THRESHOLD(VID2) 00000000
DISPC_OVL_FIFO_SIZE_STATUS(VID2) 00000800
DISPC_OVL_ROW_INC(VID2) 00000001
DISPC_OVL_PIXEL_INC(VID2) 00000001
DISPC_OVL_PRELOAD(VID2) 00000000
DISPC_OVL_FIR(VID2) 04000400
DISPC_OVL_PICTURE_SIZE(VID2) 00000000
DISPC_OVL_ACCU0(VID2) 00000000
DISPC_OVL_ACCU1(VID2) 00000000
DISPC_OVL_BA0_UV(VID2) 00000000
DISPC_OVL_BA1_UV(VID2) 00000000
DISPC_OVL_FIR2(VID2) 04000400
DISPC_OVL_ACCU2_0(VID2) 00000000
DISPC_OVL_ACCU2_1(VID2) 00000000
DISPC_OVL_ATTRIBUTES2(VID2) 00000000
DISPC_OVL_PRELOAD(VID2) 00000000
DISPC_OVL_BA0(VID3) 00000000
DISPC_OVL_BA1(VID3) 00000000
DISPC_OVL_POSITION(VID3) 00000000
DISPC_OVL_SIZE(VID3) 00000000
DISPC_OVL_ATTRIBUTES(VID3) 02008400
DISPC_OVL_FIFO_THRESHOLD(VID3) 00000000
DISPC_OVL_FIFO_SIZE_STATUS(VID3) 00000800
DISPC_OVL_ROW_INC(VID3) 00000001
DISPC_OVL_PIXEL_INC(VID3) 00000001
DISPC_OVL_PRELOAD(VID3) 00000000
DISPC_OVL_FIR(VID3) 04000400
DISPC_OVL_PICTURE_SIZE(VID3) 00000000
DISPC_OVL_ACCU0(VID3) 00000000
DISPC_OVL_ACCU1(VID3) 00000000
DISPC_OVL_BA0_UV(VID3) 00000000
DISPC_OVL_BA1_UV(VID3) 00000000
DISPC_OVL_FIR2(VID3) 04000400
DISPC_OVL_ACCU2_0(VID3) 00000000
DISPC_OVL_ACCU2_1(VID3) 00000000
DISPC_OVL_ATTRIBUTES2(VID3) 00000000
DISPC_OVL_PRELOAD(VID3) 00000000
DISPC_OVL_FIR_COEF_H_0(VID1) 00000000
DISPC_OVL_FIR_COEF_H_1(VID1) 00000000
DISPC_OVL_FIR_COEF_H_2(VID1) 00000000
DISPC_OVL_FIR_COEF_H_3(VID1) 00000000
DISPC_OVL_FIR_COEF_H_4(VID1) 00000000
DISPC_OVL_FIR_COEF_H_5(VID1) 00000000
DISPC_OVL_FIR_COEF_H_6(VID1) 00000000
DISPC_OVL_FIR_COEF_H_7(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_0(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_1(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_2(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_3(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_4(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_5(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_6(VID1) 00000000
DISPC_OVL_FIR_COEF_HV_7(VID1) 00000000
DISPC_OVL_CONV_COEF_0(VID1) 00000000
DISPC_OVL_CONV_COEF_1(VID1) 00000000
DISPC_OVL_CONV_COEF_2(VID1) 00000000
DISPC_OVL_CONV_COEF_3(VID1) 00000000
DISPC_OVL_CONV_COEF_4(VID1) 00000000
DISPC_OVL_FIR_COEF_V_0(VID1) 00000000
DISPC_OVL_FIR_COEF_V_1(VID1) 00000000
DISPC_OVL_FIR_COEF_V_2(VID1) 00000000
DISPC_OVL_FIR_COEF_V_3(VID1) 00000000
DISPC_OVL_FIR_COEF_V_4(VID1) 00000000
DISPC_OVL_FIR_COEF_V_5(VID1) 00000000
DISPC_OVL_FIR_COEF_V_6(VID1) 00000000
DISPC_OVL_FIR_COEF_V_7(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_0(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_1(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_2(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_3(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_4(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_5(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_6(VID1) 00000000
DISPC_OVL_FIR_COEF_H2_7(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_0(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_1(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_2(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_3(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_4(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_5(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_6(VID1) 00000000
DISPC_OVL_FIR_COEF_HV2_7(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_0(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_1(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_2(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_3(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_4(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_5(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_6(VID1) 00000000
DISPC_OVL_FIR_COEF_V2_7(VID1) 00000000
DISPC_OVL_FIR_COEF_H_0(VID2) 00000000
DISPC_OVL_FIR_COEF_H_1(VID2) 00000000
DISPC_OVL_FIR_COEF_H_2(VID2) 00000000
DISPC_OVL_FIR_COEF_H_3(VID2) 00000000
DISPC_OVL_FIR_COEF_H_4(VID2) 00000000
DISPC_OVL_FIR_COEF_H_5(VID2) 00000000
DISPC_OVL_FIR_COEF_H_6(VID2) 00000000
DISPC_OVL_FIR_COEF_H_7(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_0(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_1(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_2(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_3(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_4(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_5(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_6(VID2) 00000000
DISPC_OVL_FIR_COEF_HV_7(VID2) 00000000
DISPC_OVL_CONV_COEF_0(VID2) 00000000
DISPC_OVL_CONV_COEF_1(VID2) 00000000
DISPC_OVL_CONV_COEF_2(VID2) [ 141.050384] request_suspend_state: wakeup (0->0) at 141047180180 (2000-01-01 22:10:27.253875734 UTC)
00000000
DISPC_OVL_CONV_COEF_3(VID2) 0[ 141.067749] init: untracked pid 6988 exited
0000000
DISPC_OVL_CONV_COEF_4(VID2) 00000000
DISPC_OVL_FIR_COEF_V_0(VID2) 00000000
DISPC_OVL_FIR_COEF_V_1(VID2) [ 141.085754] init: untracked pid 6989 exited
00000000
DISPC_OVL_FIR_COEF_V_2(VID2) 00000000
DISPC_OVL_FIR_COEF_V_3(VID2) 00000000
DISPC_OVL_FIR_COEF_V_4(VID2) 00000000
DISPC_OVL_FIR_COEF_V_5(VID2) 00000000
DISPC_OVL_FIR_COEF_V_6(VID2) 00000000
DISPC_OVL_FIR_COEF_V_7(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_0(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_1(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_2(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_3(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_4(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_5(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_6(VID2) 00000000
DISPC_OVL_FIR_COEF_H2_7(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_0(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_1(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_2(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_3(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_4(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_5(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_6(VID2) 00000000
DISPC_OVL_FIR_COEF_HV2_7(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_0(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_1(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_2(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_3(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_4(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_5(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_6(VID2) 00000000
DISPC_OVL_FIR_COEF_V2_7(VID2) 00000000
DISPC_OVL_FIR_COEF_H_0(VID3) 00000000
DISPC_OVL_FIR_COEF_H_1(VID3) 00000000
DISPC_OVL_FIR_COEF_H_2(VID3) 00000000
DISPC_OVL_FIR_COEF_H_3(VID3) 00000000
DISPC_OVL_FIR_COEF_H_4(VID3) 00000000
DISPC_OVL_FIR_COEF_H_5(VID3) 00000000
DISPC_OVL_FIR_COEF_H_6(VID3) 00000000
DISPC_OVL_FIR_COEF_H_7(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_0(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_1(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_2(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_3(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_4(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_5(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_6(VID3) 00000000
DISPC_OVL_FIR_COEF_HV_7(VID3) 00000000
DISPC_OVL_CONV_COEF_0(VID3) 00000000
DISPC_OVL_CONV_COEF_1(VID3) 00000000
DISPC_OVL_CONV_COEF_2(VID3) 00000000
DISPC_OVL_CONV_COEF_3(VID3) 00000000
DISPC_OVL_CONV_COEF_4(VID3) 00000000
DISPC_OVL_FIR_COEF_V_0(VID3) 00000000
DISPC_OVL_FIR_COEF_V_1(VID3) 00000000
DISPC_OVL_FIR_COEF_V_2(VID3) 00000000
DISPC_OVL_FIR_COEF_V_3(VID3) 00000000
DISPC_OVL_FIR_COEF_V_4(VID3) 00000000
DISPC_OVL_FIR_COEF_V_5(VID3) 00000000
DISPC_OVL_FIR_COEF_V_6(VID3) 00000000
DISPC_OVL_FIR_COEF_V_7(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_0(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_1(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_2(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_3(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_4(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_5(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_6(VID3) 00000000
DISPC_OVL_FIR_COEF_H2_7(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_0(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_1(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_2(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_3(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_4(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_5(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_6(VID3) 00000000
DISPC_OVL_FIR_COEF_HV2_7(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_0(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_1(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_2(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_3(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_4(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_5(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_6(VID3) 00000000
DISPC_OVL_FIR_COEF_V2_7(VID3) 00000000
dsi1_regs:
DSI_REVISION 00000030
DSI_SYSCONFIG 00000011
DSI_SYSSTATUS 00000001
DSI_IRQSTATUS 000000a0
DSI_IRQENABLE 0015c000
DSI_CTRL 00efe29f
DSI_COMPLEXIO_CFG1 2a000321
DSI_COMPLEXIO_IRQ_STATUS 00000000
DSI_COMPLEXIO_IRQ_ENABLE 3ff07fff
DSI_CLK_CTRL a0306008
DSI_TIMING1 ffff7fff
DSI_TIMING2 ffffffff
DSI_VM_TIMING1 0803b009
DSI_VM_TIMING2 04141315
DSI_VM_TIMING3 03230320
DSI_CLK_TIMING 00000e0d
DSI_TX_FIFO_VC_SIZE 13121110
DSI_RX_FIFO_VC_SIZE 13121110
DSI_COMPLEXIO_CFG2 00030000
DSI_RX_FIFO_VC_FULLNESS 00000000
DSI_VM_TIMING4 00001f00
DSI_TX_FIFO_VC_EMPTINESS 1f1f1f1f
DSI_VM_TIMING5 00000000
DSI_VM_TIMING6 017c0016
DSI_VM_TIMING7 00090009
DSI_STOPCLK_TIMING 00000080
DSI_VC_CTRL(0) 20808d81
DSI_VC_TE(0) 00000000
DSI_VC_LONG_PACKET_HEADER(0) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(0) 00000000
DSI_VC_SHORT_PACKET_HEADER(0) 00000000
DSI_VC_IRQSTATUS(0) 00000000
DSI_VC_IRQENABLE(0) 000000db
DSI_VC_CTRL(1) 20808f91
DSI_VC_TE(1) 00000000
DSI_VC_LONG_PACKET_HEADER(1) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(1) 00000000
DSI_VC_SHORT_PACKET_HEADER(1) 00000000
DSI_VC_IRQSTATUS(1) 00000004
DSI_VC_IRQENABLE(1) 000000db
DSI_VC_CTRL(2) 20808d81
DSI_VC_TE(2) 00000000
DSI_VC_LONG_PACKET_HEADER(2) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(2) 00000000
DSI_VC_SHORT_PACKET_HEADER(2) 00000000
DSI_VC_IRQSTATUS(2) 00000000
DSI_VC_IRQENABLE(2) 000000db
DSI_VC_CTRL(3) 20808d81
DSI_VC_TE(3) 00000000
DSI_VC_LONG_PACKET_HEADER(3) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(3) 00000000
DSI_VC_SHORT_PACKET_HEADER(3) 00000000
DSI_VC_IRQSTATUS(3) 00000000
DSI_VC_IRQENABLE(3) 000000db
DSI_DSIPHY_CFG0 09120b0d
DSI_DSIPHY_CFG1 42030817
DSI_DSIPHY_CFG2 b8000006
DSI_DSIPHY_CFG5 e7000000
DSI_PLL_CONTROL 00000000
DSI_PLL_STATUS 00000383
DSI_PLL_GO 00000000
DSI_PLL_CONFIGURATION1 1061221f
DSI_PLL_CONFIGURATION2 00056008
dss:
DSS_REVISION 00000041
DSS_SYSCONFIG 00000000
DSS_SYSSTATUS 00000001
DSS_CONTROL 00000019
My first question is: In the board file structure, there are multiple places for putting the vertical/horizontal porches; which one matters?
How do I properly calculate the porch settings from the vendor spec above?
Currently, I do not see anything on the screen, but if I go into dsi.c and hardcode some values for DSI_VM_TIMING1 and DSI_VM_TIMING2, I can see a blue row of pixels across the long axis of the LCD.
Any help would be greatly apprciated.
