Can anyone from TI confirm that there is error in SPRUGV8C document (KeyStone Architecture DDR Memory Controller User Guide) on page 4-6.
At the bottom in the end of Table 4-5, Field PAGESIZE, written:
0 = 256-word page requiring 8 column address bits.
1 = 512-word page requiring 8 column address bits.
2 = 1024-word page requiring 8 column address bits.
3 = 2048-word page requiring 8 column address bits.
It seems to me that correct definition should be as follows:
0 = 256-word page requiring 8 column address bits.
1 = 512-word page requiring 9 column address bits.
2 = 1024-word page requiring 10 column address bits.
3 = 2048-word page requiring 11 column address bits.
Please confirm this or explain why different page size required 8 column address bits.
Thanks
