Hello,
I have a question about C6678 DDR3 controller. There is following description for DDR3 initialization.
Keystone DDR3 Memory Controller UG (SPRUGV8C)
3.2.2 Programming the SDRFC (P.51)
According to the DDR3 JEDEC standard, on reset de-assertion the DDRCKE pin must remain low for at least 500 μs before becoming active during power-up initialization. This is achieved by programming a 500 μs refresh period in the SDRFC prior to initialization.
Do you know how to process it by evmc6678l.gel? Is it possibly the following processing?
//Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0
DDR_DDRPHYC &= ~(0x00008000);
DDR_DDRPHYC |= (0x00008000);
DDR_DDRPHYC &= ~(0x00008000);
/***************** 3.4 Basic Controller and DRAM Configuration ************/
DDR_SDRFC = 0x00005162; // enable configuration
Regards
