Hello,
I have an application in which all 6 cores of the tci6486 DSP run shared code located in the SL2RAM and process data located in the external memory (DDR2).
Performing some load tests on the chip, I discovered that for some reason the load isn't similar on all the cores and I'll explain:
I have a setup in which all the cores run the same code and process the same data (each core has his own portion of data in the DDR). My test shows that the first core (core '0') has a load of 92%, while the rest of the cores (cores 1-5) have a load of 87-88%.
Another setup is similar to the setup above, except for the fact that all the cores have more accesses to the SL2RAM and DDR (due to cache misses). This time the test shows much greater variance between the cores: 87% - 94%, where the first core has the lowest core and the last core shows the highest load.
In terms of shared peripherals, I wanted to add that all the cores use the EMAC to send and receive Ethernet packets.
My question is: Is there any explanation that can explain the above? How simultaneous accesses to the SL2RAM and DDR from all the cores are handled? What's the influence on each core when all cores access the SL2RAM and DDR at the same time?
Thanks in advance,
Elad.