C6678 SGMII CDR Configuration

Daisuke,

From Table 3-136, SPRUGV9B: Gigabit Ethernet (GbE) Switch Subsystem

17-15 CDR Clock/data recovery. Configures the clock recovery algorithm.

000 = First order, threshold of 1. Phase offset tracking up to ±488ppm. Suitable for use in asynchronous systems with low

frequency offset.

001 = First order, threshold of 17. Phase offset tracking up to ±325ppm. Suitable for use in synchronous systems. Offers

superior rejection of random jitter, but is less responsive to systematic variation such as sinusoidal jitter.

010-111 = Reserved

Regards, Eric

Hi Eric,

Thank you for your reply.

Our customer is simulating for SGMII and SRIO with the AMI models.
They want to configure the SerDes Registers according to the IBIS AMI parameters.
However those details cannot be found. The SGMII specifications seem not to be public.
Therefore it is necessary to get the SGMII clock recovery algorithm details here.

Any advice or information you could provide would be greatly appreciated.

Best regards,

Daisuke

Hi Eric,

Thank you for your reply.

Yes, it will help my understanding.

I am asking the details of the AMI parameters through our local TI.

Thank you for your continuous support.

Best regards,

Daisuke