• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 98 subscribers
  • Views 347 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

c6654 timers keep running when core halted

MPiot
Intellectual 260 points

Hi,

When debugging on the c6654, the watchdog timer (and all other timers) keep running when the core is halted.  For the c6657 all cores needed to be halted for the timers to stop running, but  the c6654 only has one core so the timers should stop when it does.  I double checked and the FREE and SOFT bits for the timers are zero, so I'm at a loss at what else it could be.  Any insight into what could cause this behavior would be appreciated.

Thanks,

Mark

  • 0
    TI__Genius 12065 points

    Mark,

    Sorry for the long delay here. We are checking with our design team to see if the Timer counter could be halted in C6654. Will keep you posted once we have the feedback. Thanks.

  • 0 in reply to Steven Ji
    Intellectual 260 points

    Steven,

    Thanks for looking into this.  Have you been able to find anything yet?

    Thanks,

    Mark

  • 0 in reply to MPiot
    TI__Genius 12065 points

    Mark,

    You may already notice that in order to halt the Timer counting in emulation, no matter what setup in FREE/SOFT configuration of Timer, we have to halt all the DSP cores in the emulation, since the suspension input to the timer(s) is the AND of the suspension output from ALL DSP cores by default.

    There is one undocumented register bit that allows you to change from (the default) of AND’ing the suspension from all cores to the OR’ing the suspension of all cores.

     Register Address: 0x0262038C

                                                Reset     Reset

    Field                     Bit            Value    Description

    DSP_SUSP_CTL  31               0          Control the combination of emulation suspend signals from DSP cores

                                                                   -        0  AND suspension from all DSP cores

                                                                   -        1  OR suspension from all DSP cores

    The other bits in this register should be reserved.

    Please set bit 31 to 1 in register 0x0262038C to see if you could halt Timer counting in C6654. 

    We plan to document this feature in the next release of device data manual. 

  • 0 in reply to Steven Ji
    Intellectual 260 points

    Steven,

    Thanks, after setting that bit the timers stop during debugging on the c6654.