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Outbound Translation Region N Offset Configuration Issue Over PCIe

Joseph Furno
Intellectual 300 points

I'm having an issue configuring the Outbound Translation tables using the Region N offset Registers.  Specifically setting the OB_OFFSETn_LO bits (31:20) when configuring the Outbound Size to 8MB. 

I'm trying to set Region 0 (N=0) to the Address 0x13000000 and Region 1 (N=1) to the Address 0x13800000 over PCIe via a Root Complex processor to the Keystone C6655 configured as a PCIe  End Point.    When reading these values back I get 0x13000000 for both Regions / Translation Tables.  According to the documentation, I should be able to set bit 23 as that bit is used for both the region decoding and the address translation.

Using the emulator , we are able to change these manually....

I would appreciate any thoughts on this and suggestions on how to fix this problem.

Thanks

 

  • 0
    TI__Genius 12065 points

    In order to access those Application Registers in EP, RC will issue packets with PCIe addresses matching BAR0 of EP, and you access the OB_OFFSET_INDEX0 and OB_OFFSET_INDEX1 registers in EP with offset 0x200 and 0x208, is it correct?

    When you connect emulator to EP (C6655) after RC modifies those registers, what values are in those two OB offset registers of EP please?

    Will them be both 0x13000000 or 0x13800000 in the second register? And is RC able to update the other OB offset registers except INDEX0 and INDEX1 please?

    I think there should be no limitation on EP side to accept the changes of OB offset registers from RC. We probably could check if RC accesses EP correctly first.