about am335x lcd driver Hsync and Vsync

Zhiquan Li,

Can you share your register settings for RASTER_CTRL, RASTER_TIMING0, RASTER_TIMING1, and RASTER_TIMING2?

-Tyler

Zhiquan,

It looks like your diagram shows that the width of the VSYNC pulse is 3 lines wide. The width of your VSYNC pulse can be programmed using the VSW field of the RASTER_TIMING1 register.

If you're looking for HSYNC and VSYNC to transition on the same clock edge, unfortunately that is not possible with the AM335x. You can configure the LCDC to have VSYNC and HSYNC transition on the same type of edge, falling for example, however they will not transition on the exact same edge. There will be a minimum of 1 PCLK cycle between the two transistions.

-Tyler

I am observing the same behaviour here!

In Figure 5-82 "LCD Raster-Mode Active", the start of HSYNC is at the same time as the start of VSYNC.

This is the expected behaviour.

We are using a TFT LCD with has negative VSYNC and HSYNC, so we set IHS and IVS in RASTER_TIMING_2.

The observed behaviour is that VSYNC is starting at the rising edge of HSYNC. It should start at the falling edge of HSYNC!

The effect is that the first visible line of the framebuffer is not displayed, and at the bottom of the screen is a line filled with garbage (last pixel content from previous line).

Workaround is:

VBP = VBP + 1

VFP = VFP - 1

This error should be documented in the errata sheet!

regards

Wolfgang

Hi TI team,
Please see the Figure 7-82 in AM335x datasheet.
HSYNC and VSYNC are to transition on the same clock edge.
is the datesheet wrong?

AM335x Sitara™ Processors (Rev. H)

Figure 7-82. LCD Raster-Mode Active