• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 98 subscribers
  • Views 494 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Edma3 lld memory footprint cache coherency

ilay nissim
Intellectual 530 points
Other Parts Discussed in Thread: TMS320C6678

Hello

We saw that the lld memory footprint was 2 big for us.

For this reason and some other reasons, we take the lld & rm files and compile them\

we would like to move big global array such as those defined in edma_init.c in edma3resmgr.c edma3_drv_init.c edma3_rm_gbl_data.c edma_c6678_cfg.c to DDR

The questions is, how does the lld handle cache coherency to those array's?

we couldn't see cache alignment / cache line sized buffer for those array

how does the lld handle l1 and l2 cache coherncy for it's own array's used for managment?

Is there a better way to reduce L2 memory consumption of the driver?

Tks

Ilay

  • 0
    TI__Mastermind 30825 points

    Itay,

    I'm not sure what you mean by the LLD memory footprint is too big.  Maybe you have a bunch of pre-generated PaRAM entries that you want stored some where.

    I'm not sure by what you mean when you ask about the LLD handling cache coherency of those array's.  Can you give me specific details about what array's you're referring to. Are you talking about PaRAM entries, how are things being accessed (EDMA accesses or CorePac accesses.)

    Regarding how the cache behaves.  It would be best for you to review the C66x Cache User Guide which is located in the TMS320C6678 <- Product Page.

    Best Regards,
    Chad 

  • 0 in reply to Chad Courtney
    Intellectual 530 points

    Hello Chad,

    about lld memory consumption...

    We saw lld consume a lot of L2 memory.

    looking into the files we found a few big arrays.

    I am referring to arrays such as :

    in edma_cfg.c : edma3GblCfgParams, defInstInitConfig

    in edma3_drv_init.c drvObj, drvInstance, edma3DrvChBoundRes

    in edma3_rm_gbl_data.c userInstInitConfigArray, resMgrInstanceArray 

    in edma3resmgr.c resMgrObj, edma3DmaChTccMapping

    Our intention is to reduce memory footpring by moving  these array's to DDR.

    About Cache: 

    our concern is since many core use the lld driver (c6678 is the device)

    are there issue cause those arrays are not L1d or L2 cache line aligned (and are not a multiple of cache size)

    (I read the Cache user guide a few times.)

    Tks

    Ilay

  • 0 in reply to ilay nissim
    TI__Mastermind 30825 points

    Yes, these can reside in DDR.   There are no caching issues with doing so.  Only things that are shared in which you modify them and another corepac reads them would you need to worry about coherence issues.  If this is the case, you can simply peform cache writeback/invalidates to force it out of the local cores back to external memory.

    That said the items that are arrays here tend to be one time program items during the overall configuration.

    There's no issues w/ alignment.  

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Intellectual 530 points

    Chad During some of the array's are accesed in run time for example

    Channel open / setup / start

    in channel open

    The lld Reads and than writes to rmInstance->avlblDmaChannels 

    this is shared by all cores, (right?)

    so it can happen that

    core 0 writes this line and core 1 reads this line