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C6655 Teranet traffic

UNA
Mastermind 7980 points
Other Parts Discussed in Thread: TMS320C6655

Hi,

I have questions about Teranet on C6655 device.

 

Q1) When SRIO access L2 RAM during EDMA transfer of 192byte data to L2 RAM from EMIF16,     does SRIO tranfer wait for EDMA transfer until the end ?

Q2) When SRIO access L2 RAM during CPU transfer of 192byte data to L2 RAM from EMIF16,     What is the behavior ?

    a. After the transfer of SRIO is complete, to accsess EMIF16 ?

    b. EMIF access does it take place in the middle of the SRIO transfer ?

 

Best regards,

Chi

  • 0
    TI__Mastermind 30825 points

    Chi,

    The transfers will happen simultaneously.

    The EDMA has many high bandwidth paths, that can operate in parallel.  The L2 Access Rate is much higher than either SRIO or EMIF16 could consume, and the accesses are interleaved instead of being held off as you'd indicated.

    If there were multiple interfaces accessing an L2 SRAM such that it doesn't have the capacity to serve all of them at the same time, then Bandwidth Management, as described in the C66x CorePac User Guide, would be used (This document can be found on the TMS320C6655 <- Product Page.)  It will prioritize based on the Priority level of the requester, but also uses the MAXWAIT feature to ensure that at least some of the data from lower priority transfers are making it through instead of waiting until the higher priority has fully completed.

    Best Regards,
    Chad