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questions about L1D, MAR and cache coherence on C6657

Weichun Yuan
Expert 1210 points

We use C6657 to talk with our host processor through PCIe. We enabled cache (L1D, L1P and L2). We put the communication buffer in a buffer in none-Cache DDR by zeroing MAR128. Do we have to manually maintain cache coherence for L1D during PCIe communication (write back when core write and invalidate before core read?)

SPRUGW0b-1 section 4.4.4 says that "L2 memory includes a set of registers to define the cacheability of external memory space". Does that mean that MARn only affects L2 cache, and if we use data range with corresponding MARn=0, we still have to manually control L1D?

thanks

Weichun

  • 0
    TI__Guru** 116170 points

    Hi Weichun,

    The cache coherence operations on L1D are only required if DMA/Other writes code to L2 SRAM or CORE modifies code in L2 SRAM. In your use case, do you have any DMA activity from DDR to L2 ? 

    Regards,

    Rahul

    PS: Please also look at the scenarios described in L2 and L1 Cache coherency sections of the C66x Cache user guide.

  • 0 in reply to Rahul Prabhu
    Expert 1210 points

    Rahul,

    yes, it is some flag used for handshaning. Both pcie and core read and write to this variable in DDR as well as read it, of course at different stages of the handshaking operation. Those variables are in DDR with corresponding MARn (in particular MAR128) set to be 0 while we globally enabled L1D, L1P and half of L2.

    Do we have to do explicit L1D writeback after core writes and L1D invalidate before core reads? Is the MARn applicable to L2 only or to all the caches?

    thanks

    Weichun

  • 0 in reply to Weichun Yuan
    TI__Mastermind 23525 points

    Weichun,

    As Rahul mentioned, you only need the L1D cache coherency commands if other masters are writing to L2 space, local or shared L2, because by default these areas are cached.  If you have a variable in DDR, and the MAR for that address range is disabled, then when the CPU does a read to that address, it will read from DDR.  Likewise a write to that address will be directly to the DDR space. Page 1 -8 of http://www.ti.com/lit/ug/sprugy8/sprugy8.pdf says:

    The cacheability settings of external

    memory addresses (through the MAR bits)
    only affect L1D and L2 caches on C66x devices; that is, program fetches to
    external memory addresses are always
    cached in L1P, regardless of the
    cacheability setting. This is not the ca
    se on C64x devices, where the settings
    affects all caches, L1P, L1D, and L2.

    Regards,

    Travis