Used EDMA channels in Appro IPNC rdk 3.0 (McFW)

Hi Roei,

1. EDMA engine has 4 Transfer controllers(TC) and each TC has a queue.For every EDMA channel you can program as to which queue the transfer request should be submitted to.There is priority setting amongst the 4 queues and based on EDMA usage in the system you should distribute the channels among the queues.
2. Each EDMA master can operate under a different shadow region.DSP can work under shadow regions 2-7. 
3. Yes all the channels are shared by all the EDMA masters, there are some channels tied to events like SD card receive/transmit which cannot be used by the system.
4. Linking EDMA channels is done using the spare PaRAM entries,on expiry of the channel PaRAM entry if linked it automatically gets loaded with the contents of linked PaRAM entry.The linked PaRAM entry can have different source and destination addresses so that when the current transfer completes immediately transfer programmed in lined PaRAM entry is triggered.

regards,

Anand

Hi Anand, thanks for the support but is it possible to be more specific regarding what s/w or h/w block is using the EDMA channels (i.e. reserve them)?

I couldn't find any specific documentation and when I use some IDs freely, the system hangs on occasion. Parts of the system is w/o source (only libs) so how can one know what is for spare and what isn't?

Regards,

Roei

Hi Roei,

To find out the free EDMA channels,on A8 side you can call the API 'OSA_dmaOpen()' in a loop for 64 times and note the free channels it is giving out.This will be only test code.

You can use all the free EDMA channels returned by above call on any of the cores (A8,M3,DSP).

Going forward we are going to allocate EDMA channels only through above call.

regards,

Anand

Hi Anand, thanks for the fast response - just to make sure: Is this API call will tell me what is opened at the moment? If that's the case what might happen if someone is using the EDMA like I do, in an ad-hoc fashion, this might result in a timing issue i.e. maybe when I'll perform my test I will see channel id 3 (w/o loss of generality) as free but at some other point it will be used.

If I want to work in a dynamic mode, so that my algorithm will use only the currently free channel, is there a mean in DSP core (Bios6) to perform this OSA_dmaOpen query (which uses IOCTL commands)? Also, my idea cannot ensure that other modules are "nice" like me and perform this query so contention might still occur.

Regards,

Roei 

Adding to my last question (which wasn't responded as of yet), I found the file /Source/ipnc_rdk/ipnc_mcfw/mcfw/src_bios6/utils/src/utils_dma_common_cfg.c that seems to hold some info regarding EDMA usage all across the system but there's a comment that suggests this is an omap device mapping:

HOST A8 - Defined in <linux kernel>\arch\arm\mach-omap2\devices.c, ti81xx_dma_rsv_chans, ti81xx_dma_rsv_slots,

but I'm working with Da-Vinci device (8148). I went further into the Linux end and looked inside:

/Source/ti_tools/ipnc_psp_04_04_00_01/kernel/arch/arm/mach-davinci/include/mach/edma.h

Somehow, this is the closest thing I've found which is related to EDMA channels usage (partial quoting):

#define DAVINCI_DMA_MCBSP_TX 2
#define DAVINCI_DMA_MCBSP_RX 3
#define DAVINCI_DMA_VPSS_HIST 4
#define DAVINCI_DMA_VPSS_H3A 5
#define DAVINCI_DMA_VPSS_PRVU 6
#define DAVINCI_DMA_VPSS_RSZ 7
#define DAVINCI_DMA_IMCOP_IMXINT 8

....

#define DAVINCI_DMA_PWM0 52
#define DAVINCI_DMA_PWM1 53
#define DAVINCI_DMA_PWM2 54

but this is also strange as channel id 6 and 8 are usage in FD, VA respectively in DSP.

I'm asking again - who's responsible in TI's support to describe what can be used and what can't... ?

Regards,

Roei

Hi Anand, I've made the test of  OSA_dmaOpen x64 calls in several places in my flow but the IDs reported aren't constant so this suggests that the channels are being somehow opened and then closed by a user. I can't really rely on such info as I need to use channels that I can be sure are mine alone to use.

Also, even if I make some OR logic and extract from several runs IDs that were never used by Linux, who can tell what VPSS and all bios6-M3 code is using?

I must say that I find it very strange there isn't some single direct map of used channels, after all, someone had to bring-up the Appro device and validate the system functionality, no?

Any thoughts of why I get non-constant free channels IDs?

To avoid confusion, this is the code I was using for finding the relevant free channels:

#define BITS64_1(n) ( 1ll << (n) )

static void PrintFreeEdmaChannels()
{
  OSA_DmaChHndl dmaHndl;

  int status;

  status = OSA_dmaInit();
  uint32 i;
  uint64 dmaBit = 0;
  if (status == 0)
  {
     for (i = 0; i < 64; i++)
     {
        status = OSA_dmaOpen(&dmaHndl, OSA_DMA_MODE_NORMAL, 1);
        if (status != 0)
        {
           OSA_printf("%s:OSA_dmaOpen %u failed - %d\n", __func__, i, status); 
        }
       else
       {
         // OSA_printf("%s:OSA_dmaOpen passed with ch id = %d\n", __func__, dmaHndl.chId);
         dmaBit |= BITS64_1(dmaHndl.chId);
       }
    }
  }
  else
  {
      OSA_printf("%s:OSA_dmaInit failed - %d\n", __func__, status);  
   }

  for (i = 0; i < 64; i++)
  {
     if ((BITS64_1(i) & dmaBit) == 0)
     {
         OSA_printf("OSA_dmaOpen free for bios6 = %u\n", i);
     }
  }

}

Regards,

Roei

Hi Roei,

I will check the code and get back to you.

regards,

Anand

Hi Roei,

Static allocation of EDMA channels is done in the kernel using the following info:

• static const s16 ti814x_dma_rsv_chans[][2] = { /* (offset, number) */
   {0, 2},
   {5, 4},
   {14, 2},
   {26, 6},
   {48, 4},
   {56, 8},
   {-1, -1}
  };
• Events on devices like McASP,SPI which needs to be tied to EDMA channels will requrest EDMA channels using the flag 'IORESOURCE_DMA' in devices.c file in kernel.

The remainig channels are free and can be dynamically allocated to the user.

When we call OSA_dmaOpen() API a free available channel is given to you and is marked as not available.
So if you call the loop multiple times then you will surely get different values.

So the thumb rule for using the EDMA channels is:

• On A8 use OSA_dmaOpen() API
• For M3 and DSP usage, reserve the required no of channels in ti814x_dma_rsv_chans structure then use them on M3 and DSP.While reserving make sure not to conflict with the channels used for devices (IORESOURCE_DMA).

This is how we have been using EDMA channels on M3 and DSP.

regards,
Anand

First, Anand, let me say thanks for your quick support. I feel like I understand most of the issues I've queried but the M3 size is still a bit vague. The IPNC Appro device is a demo kit with many features. What ensures me under, let's say, the video / capture / display that they don't use EDMA channels from this free list? I looked freely over the code and couldn't find some link / ti_tools code that is using directly the EDMA - does this means that I can use all the free ones w/o fearing I will have some conflict?

If that's the case then I'm done else it would be nice to have some mean (code, contact person, doc) that state the M3 used channels. What about the OSD windows, I would think those also use DMA for fast block copy...

Regards,

Roei