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Question about cache on C6657

Jing Bai
Intellectual 650 points
Other Parts Discussed in Thread: TMS320C6657

Hi sirs,

I have a question about CACHE on C6657.

L1D & L1P on both core 0 & 1 are set as CACHE mode. I figured that MSMCSRAM could be cache in L1D & L1P.

Core 1 is accessing MSMCSRAM with real time. At the same time, Core 0 is also reading from MSMCSRAM too.

May I know why the refreshed data at Core 0 is slower than the Core 1?

Thank you in advance.

Regards,

bai

  • 0
    TI__Mastermind 30825 points

    Can you be more specific about what you're doing?  Reads and Write access by the CorePac# to/from MSMC?

    If you're modifying MSMC by CorePac#, and it was resident in CorePac#'s L1D, it will reside in L1D until it's evicted/written back to MSMC.

    Also, if CorePacX is reading data that CorePacY had written to MSMC and CorePacX currently has that space cached into L1D, it will not re-read the MSMC until that data is evicted.

    Coherence to External memory's (MSMC is external to the CorePacs) needs to be maintained by the SW.  

    This is stated and other items are detailed in the C66x Cache User's Guide which is available on the TMS320C6657 <- Product Page.

    Best Regards,
    Chad