Hi sirs,
I have a question about CACHE on C6657.
L1D & L1P on both core 0 & 1 are set as CACHE mode. I figured that MSMCSRAM could be cache in L1D & L1P.
Core 1 is accessing MSMCSRAM with real time. At the same time, Core 0 is also reading from MSMCSRAM too.
May I know why the refreshed data at Core 0 is slower than the Core 1?
Thank you in advance.
Regards,
bai