AM1808 Underclocking

Daisuke Maeda

Guru 20345 points

Other Parts Discussed in Thread: AM1808, OMAPL138

Our customer uses the 375MHz device of AM1808. They want to operate it at 250MHz.

Is the minimum frequency defined for each system clock?

For the PLL0_SYSCLK2:

"Important Notice: The USB0 controller module clock (PLL0_SYSCLK2) must be greater than 30 MHz for proper operation of the USB controller. A clock rate of 60 MHz or greater is recommended to avoid data throughput reduction."

AM1808 ARM Microprocessor (Rev. C)
http://www.ti.com/lit/ds/sprs653c/sprs653c.pdf
5.20 Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG] - Page 176

For other system clock, is it defined?

Best regards,

Daisuke

over 12 years ago

0 Mukul Bhatnagar over 12 years ago

TI__Guru* 85085 points

In general apart from USB and DDR , both of which have the min frequency limitations noted in the datasheet, I do not think there is a minimum "internal" frequency limit for other peripherals and CPU. If you reduce the SYSCLKs/ Device speed, it will have impact on IO clocks that are derived from internal module clocks, in which case the system integrator should keep in mind the min IO clock frequency for the devices interfaced to the processor.

0 Daisuke Maeda over 12 years ago in reply to Mukul Bhatnagar

Guru 20345 points

Hi Mukul,

Thank you for your reply.

Mukul Bhatnagar said:

In general apart from USB and DDR , both of which have the min frequency limitations noted in the datasheet,

Is that for DDR Table 5-23 in the datasheet?

Best regards,

Daisuke

0 Raja over 12 years ago in reply to Daisuke Maeda

TI__Guru* 81335 points

Hi Daisuke,

Daisuke said:
Is that for DDR Table 5-23 in the datasheet?

Yes.

Minimum frequency for SATA interface also defined in Table 5-47.

Thanks.

0 Daisuke Maeda over 12 years ago in reply to Raja

Guru 20345 points

Hi Rajasekaran K,

Thank you for your reply.

Best regards,

Daisuke

0 Sivaraj Kuppuraj over 12 years ago in reply to Daisuke Maeda

TI__Mastermind 35645 points

Hi Daisuke,

Likewise, for McBSP module, there are minimum CLKR/X cycles needs to be met even when CLKR/X is generated by an internal clock source and this parameter applies to the maximum McBSP frequency.

Please refer Table 5-57 & 5-58 for timing requirements of McBSP0 and Table 5-61 & 5-62 for timing requirements of McBSP1 in the datasheet below:

http://www.ti.com/lit/sprs590

Thanks & regards,

Sivaraj K

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0 Mukul Bhatnagar over 12 years ago in reply to Daisuke Maeda

TI__Guru* 85085 points

Daisuke-san

Table 5-25 in the latest OMAPL138 datasheet on the web has the DDR2/mDDR min limits at each OPP.

Regards
Mukul

0 Daisuke Maeda over 12 years ago in reply to Sivaraj Kuppuraj

Guru 20345 points

Hi Sivaraj K,

Thank you for your reply.

Did you not say minimum CLKR/X cycle time?

I worry about maximum cycle time.

Best regards,

Daisuke

0 Daisuke Maeda over 12 years ago in reply to Mukul Bhatnagar

Guru 20345 points

Hi Mukul,

Thank you for your reply.

I checked Table 5-23 in the AM1808 data sheet.

Best regards,

Daisuke

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