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EDMA UART Event

Stefan Eichenberger
Prodigy 100 points

Hello

We want to use the EDMA for a UART transfer operation. We've configured the EDMA so that it transmits one byte, each time a byte is received. The problem is now that it stops when another driver uses the DMA.

My specific question is now if the following theory can be correct (FIFO trigger level = 1):

  1. The UART receives one byte and fires an event to the DMA.
  2. The DMA is currently blocked, because another transfer is running. The event gets Queued.
  3. A second byte receives the UART, the byte is stored in the FIFO. No new event is triggered, because the trigger level was already achieved.
  4. The DMA finished the other transfer, and copies the byte from the DMA to the local memory.
  5. Nothing else happens, because the UART still signalizes that there are some bytes to transfer, but no new event will be send.
So is it possible that the UART only triggers an event if the trigger level is reached? And it does not trigger more events if the trigger level is still reached but the event was already send? Is this the same for the "receiver time-out" event?
Thanks for the answer and best regards,
Stefan
  • 0
    TI__Mastermind 35645 points

    Hi Stefan,

    Thanks for your post.

    Basically, the UART will not indicate when the receiver FIFO trigger level is reached or when a receiver time-out occurs. When the receiver FIFO reaches a trigger level of 1, 4, 8 or 14, UARTn_RTS signal will be deasserted, the sendiing UART will send an additional byte after the trigger level is reached by assuming that, it has another byte to send, because, it is not aware that UARTn_RTS is deasserted until after it has started sending the additional byte.

    So, to answer your question posted above,

    It is not possible for UART to trigger any new events once the trigger level is reached and it stops receiving data. Events will be sent only for the UART received bytes and it gets queued up since DMA is engaged with another transfer in your case. UARTn_RTS will be reasserted only if the receiver FIFO is emptied for trigger level 1, 4 and 8.

    Yes, it is the same situation for receiver time-out  too.

    You can also enable UART Interrupt request RDAINT (receive data-ready interrupt) in IER when trigger leve is reached in the FIFO mode by setting the ERBI bit and it will be recorded in IIR. Receiver FIFO trigger level (RXFIFTL) bit fields in FCR (FIFO control register) sets the trigger level for the receiver FIFO.

    All the above details shall be referred in C6748 DSP TRM as below:

    http://www.ti.com/lit/spruh79

    Please refer Sections 30.2.5.4.1, 30.2.8,2 (Table 30-5) & 30.3.5 (Table 30-12) in the above TRM.

    Thanks & regards,

    Sivaraj K

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  • 0 in reply to Sivaraj Kuppuraj
    Prodigy 100 points

    Thanks for the fast response!

    Regards,
    Stefan