• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 99 subscribers
  • Views 673 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

512MB SDRAM Support with OMAP3 WinCE6.0 BSP

James Li
Intellectual 750 points
Other Parts Discussed in Thread: DM3730

Hello All,

I have some issues with 512MB SDRAM support with OMAP3 WinCE6.0 BSP. I have read some discussions in the forum but I'm still facing the problem.

Our customized board is very close to Mistral EVM. Now we have two 256MB (32bit) DDR RAM connected to sdrc_cs0 and sdrc_cs1 respectively.

The register values for some SDRC registers are:

SDRC_MCFG_0 = 0x3588099

SDRC_MCFG_1 = 0x3588099

SDRC_MR_0 = 0x32

SDRC_MR_1 = 0x32

SDRC_CS_CFG = 0x2

which mean cs0 addresses SDRAM chip1 from 0x80000000-0x8fffffff and cs1 addresses 0x90000000-0x9fffffff.

I have used the same in Android and Android works fine.

I understand that I need to modify some files in WinCE6.0 BSP to make 512MB work.

The following is what I did:

1. In image_cfg.h

#define DEVICE_RAM_SIZE                 0x20000000
#define IMAGE_WINCE_RAM_BANK1_SIZE    0x16600000   // RAM (2nd BANK)  102 MB + 256 MB

2. in platform.c

DDR_DEVICE_PARAM BSP_DDR_device_params[2]=
{
    /* MICRON DDR */
   {
       (UINT32)BSP_MICRON_SDRC_MCFG_0,
       (UINT32)BSP_MICRON_SDRC_MCFG_1,
       (UINT32)BSP_MICRON_SDRC_ACTIM_CTRLA_0,       
       (UINT32)BSP_MICRON_SDRC_ACTIM_CTRLB_0,       
       (UINT32)BSP_MICRON_SDRC_ACTIM_CTRLA_1,   
       (UINT32)BSP_MICRON_SDRC_ACTIM_CTRLB_1,       
       (UINT32)BSP_MICRON_SDRC_RFR_CTRL_0,
       (UINT32)BSP_MICRON_SDRC_RFR_CTRL_1,
   },
   
    /* HYNIX DDR */
   {
       (UINT32)BSP_HYNIX_SDRC_MCFG_0,
       (UINT32)BSP_HYNIX_SDRC_MCFG_0, // MCFG_0 and MCFG_1 are the same
       (UINT32)BSP_HYNIX_SDRC_ACTIM_CTRLA_0,
       (UINT32)BSP_HYNIX_SDRC_ACTIM_CTRLB_0,       
       (UINT32)BSP_HYNIX_SDRC_ACTIM_CTRLA_1,
       (UINT32)BSP_HYNIX_SDRC_ACTIM_CTRLB_1,
       (UINT32)BSP_HYNIX_SDRC_RFR_CTRL_0,       
       (UINT32)BSP_HYNIX_SDRC_RFR_CTRL_1,        
   }
};

I know I also need to modify addrtab_cfg.inc but I don't know how to do it properly.

My current addrtab is

    DCD     0x80000000, 0x80000000, 256     ; SDRAM
    DCD     0x93000000, 0x13000000,  16     ; CS3, LAN9115    
    DCD     0x94000000, 0x14000000,  16     ; CS4, QUART       
    DCD     0x95000000, 0x15000000,  16     ; CS5,
    DCD     0x96000000, 0x48000000,  16     ; L4 Core/Wakeup registers
    DCD     0x97000000, 0x49000000,   1     ; L4 Peripheral
    DCD     0x97100000, 0x68000000,  16     ; L3 registers
    DCD     0x98100000, 0x6C000000,  16     ; SMS registers
    DCD     0x99100000, 0x6D000000,  16     ; SDRC registers
    DCD     0x9a100000, 0x6E000000,  16     ; GPMC registers
    DCD     0x9b100000, 0x40200000,   1     ; 64KB SRAM
    DCD     0x9b200000, 0x5C000000,  16     ; IPSS interconnect
    DCD     0x9C200000, 0x00000000,   1     ; ROM
    DCD     0x9C300000, 0x08000000,   1     ; NAND Registers (FIFO) and
    DCD     0x00000000, 0x00000000,   0     ; end of table

If I changed SDRAM size to 512, I need to change the register mapping also. But both OEMAddressTable and config.bib must fall between 0x80000000 and 0xA0000000. Then how can I map the registers to virtual memory.

If I used current settings and rebuilt everything, The OS hangs after EnumExtensionDRAM.

Would anyone give me some advice on this issue?

Thanks,

James

  • 0
    Intellectual 750 points

    I think I have it figured out. The whole 512MB virtual memory cannot be mapped to SDRAM only.  We should map some to registers which means we will have less number of SDRAM mapped.

    Thanks,

    James

  • 0 in reply to James Li
    Genius 5470 points

    This is true . With WEC 7 you can actually map the entire 512MB (and more) to RAM as the improved kernel allow separate MMU mapping space for ARM registers.

  • 0 in reply to DavidVescovi
    Expert 2280 points

    Hi David,

    I use WEC7 and latest Adeneo BSP for my DM3730 board, which has 512MB DRAM.  However, when using static mapping in addrtab_cfg.inc, the actual RAM size that can be used is only 410MB; 102MB is for other things.  I have been trying different ways to get the entire 512MB but without success.  One way I try is to use both static and dynamic mappings as followings:

    g_oalAddressTable
    DCD 0x80000000, 0x80000000, 256
    DCD 0x99A00000, 0x15000000, 2 ; CS5, LAN9115
    DCD 0x99C00000, 0x48000000, 16 ; L4 Core/Wakeup registers
    DCD 0x9AC00000, 0x49000000, 1 ; L4 Peripheral
    DCD 0x9AD00000, 0x68000000, 16 ; L3 registers
    DCD 0x9BD00000, 0x6C000000, 16 ; SMS registers
    DCD 0x9CD00000, 0x6D000000, 16 ; SDRC registers
    DCD 0x9DD00000, 0x6E000000, 16 ; GPMC registers
    DCD 0x9ED00000, 0x40200000, 1 ; 64KB SRAM
    DCD 0x9EE00000, 0x5C000000, 16 ; L3 Interconnect View of IVA2.2
    DCD 0x9FE00000, 0x00000000, 1 ; ROM
    DCD 0x9FF00000, 0x08000000, 1 ; NAND Registers (FIFO)
    DCD 0x00000000, 0x00000000, 0 ; end of table

    and in init.c,

    RAMTableEntry g_RamTableEntry[2] = {
    {(0xA0000000) >> 8, 256 * 1024 * 1024, 0},
    {(0xB0000000) >> 8, 0, 0}
    };

    RamTable g_RAMTable = {MAKELONG(CE_MINOR_VER, CE_MAJOR_VER),
    sizeof(g_RamTableEntry) / sizeof(g_RamTableEntry[0]), g_RamTableEntry};

    With the configurations above, my board hung during boot-up.  However, when I change the table to

    RAMTableEntry g_RamTableEntry[2] = {
    {(0x90000000) >> 8, 256 * 1024 * 1024, 0},
    {(0xA0000000) >> 8, 0, 0}
    };

    the boot-up did not hang but the amount of RAM as seen in the Control Panel is about the same as in the static mapping case.

    Would you please tell me why it does not work when I set the starting address for the second half of DRAM at 0xA0000000?  Can you show me how to get the entire 512MB RAM?  Have you ever used OALDeviceTable for this purpose?

    Thanks,

    Luan