Hi all,
I am using the Cortex A8 processor in DM8168 and have some troubles in reading timer count TCRR.I did an experiment to test the reading latency of TCRR register. After initializing timer, I read TCRR register several times in a for-loop. From assembly I confirmed that only 1~2 instructions are executed between each reading of TCRR with LDR. These instructions are all register related operations and should have little latency. I also confirmed that timer is configured as POSTED mode and using 27MHz clock.
What I learned from document is that in POSTED mode, reading TCRR involves only one OCP interface reading request without extra re-synchronization with timer clock. Because OCP clock is 400MHz and timer clock is 27MHz in my configuration, I expected that multiple reads of TCRR should get opproximately the same values, with the difference of at most 1.
However I found the difference of each reading result is about 4~5. This means each read of TCRR have a latency of about 15-18us, which is too large for 400MHz OCP clock. I also repeated the same test in non-POSTED mode, and the reading result difference is 7, which is also much larger than the value on document (3 OCP clock + 2.5 TIMER clock).
The Cortex A8 is running at 1GHz and instructions are located at 800MHz DDR with both I-cache and D-cache enabled. So I can not think out a reason for such a large latency. Am I mis-understand something?