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C6678 PCI Express x2 lane length matching requirement

Simon Pack
Expert 1660 points
Other Parts Discussed in Thread: TMS320C6678

I have a c6678 design which has x2 PCIe.

Reading the hardware design guide (SPRABI2B) Section 4.3.3 states that the receive pairs should be skew matched to within 5pS and the transmit pairs skew matched to within 10pS. What does this mean ?

It implies that the data on the two lanes have to be closely time aligned (almost as if the clock recovery on lane 0 is used to sample the data eye on lane 1). This would be ridiculous. PCIe normally doesn't have a tight time alignment requirement between different lanes.

What is the actual skew matching tolerance requirement between the two lanes for the C6678?

 

  • 0
    TI__Guru**** 178076 points

    Simon

    Please refer to the Keystone II Architecture Serializer/Deserializer (Serdes) User Guide (SPRUHO3) section 8.2 for PCIe layout constraints:

    • Each complementary PCIe SerDes receive pair shall be individually skew matched to within 1 ps. 1 ps equates to approximately 5.464 mils to 7.092 mils (depending on propagation delays). Example of complementary pairs include PCIERXN0 & PCIERXP0.

    • Each complementary PCIe SerDes receive pairs shall be routed on the same layer.

    • Each complementary PCIe SerDes transmit pair shall be individually skew matched to within 1 ps. 1 ps equates to approximately 5.464 mils to 7.092 mils (depending on propagation delays). Example of complementary pairs include PCIETXN0 & PCIETXP0.

    • Each complementary PCIe SerDes transmit pairs shall be routed on the same layer.

    • All complementary PCIe receive pairs PCIERXN/P1:0 shall be assigned to an individual net class where routing skew shall not be greater than 100 ps between all receive pairs. (The full link budget is 2UI+500ps so lane to lane skew can be larger if additional system analysis is completed.)

    • All complementary PCIe transmit pairs PCIETXN/P1:0 shall be assigned to an individual net class and routing skew shall not be greater than 100 ps between all transmit pairs. (The full link budget is 2UI+500ps so lane to lane skew can be larger if additional system analysis is completed.)

    • Transmit and receive signals must be referenced to parallel ground planes.

    • Vias are allowed and should never exceed four per net, all nets must be balanced and the impact of the via on timing, reflections, and loading taken into account during design and layout. This interface should be modeled to assure functionality.

    • Differential signal routing must achieve a 100-ohm differential impedance.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Expert 1660 points

    Hi David,

    Many thanks for your answer about Keystone II devices. However, my question was about TMS320C6678 which is Keystone I.

    I have also found document SPRABC1 section 7.2 has the tighter tolerance requirement of 5pS.

    Are you telling me that documents SPRABI2B and SPRABC1 are both incorrect, and the Keystone II document should be used for the C6678 ?

    Thanks,

    Simon

  • 0 in reply to Simon Pack
    TI__Guru**** 178076 points

    Simon

    This is correct, the PCIe layout constraints listed in Keystone II document should be used for the C6678.  

    Thanks

    David