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Can EDMAs separate in real time the lines of an interlaced image?

Keith Nusekabel
Prodigy 50 points
Other Parts Discussed in Thread: TMS320DM643

Can EDMAs be used to separate in real time the lines of an interlaced image as the image is received without processor core interaction?

A proposed design that I have been asked to examine will be providing what I think can be best described as an interlaced image where odd lines of image data are for 1 group of light frequencies and the even lines of data are for another group of light frequencies.  Part of the objective for capturing this data is to separate the odd line data from the even line data into separate buffers in RAM for post capture processing by the DSP.  The start of each line (odd and even) will be indicated by an external interrupt (EXT_INT7), and odd lines of data should be transferred to one buffer with incrementing addresses and even lines of data should be transferred to another buffer with incrementing addresses.  The source of the data is to be a static FIFO address (part of an FPGA) which can only hold one line's worth of data.  Each line of data is approximately 800 bytes and the total (odd plus even) number of lines will be approximately 600.

The EDMAs seem to have considerable flexibility and the goal that I am seeking seems like something that should be within the capabilities of the EDMAs, but I cannot envision a technique for configuring the EDMAs to accomplish this goal.  I have examined "Linking EDMA Transfers" as documented in SPRU234C, but I do not think that method will provide the incrementing destination addresses needed for each odd or even line of data.  I have also examined "Chaining EDMA Channels" as documented in SPRU234C, but with the same interrupt being used for synchronization of each line of odd and even data it appears that chaining will not work.  (Separate interrupts for the odd and even lines of data are not available without redesigning a circuit board and cramming additional functionality into the FPGA.)

Ideas and suggestions on how to accomplish this separation of data would be appreciated.

I am new to this forum and to TI DSPs.  Any help is appreciated.

Thank you,

Keith

  • 0
    TI__Mastermind 20790 points

    Keith,

    Welcome to the TI E2E forum. I hope you will find many good answers here
    In addition you can find some details through the TI.com documents and the TI Wiki Pages.
    Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics.

    Will you provide some more working environment details,
    Are you using which TI processor?

  • 0 in reply to Pubesh
    Prodigy 50 points

     

    Pubesh,

    Thank you for the prompt response.

    I have searched this forum and gone through TI Wiki pages and could not find a similar example or question.

    The processor in use is TMS320DM643.  This processor has 64 EDMA channels.  The current system does us the EDMAs for data transfer, but the techniques currently in use do not apply to this issue for the reasons cited in the initial post.

    We are using Code Composer 3.0.

    Are there other details that are needed ?

    Thank you,

    Keith

     

  • 0 in reply to Keith Nusekabel
    TI__Mastermind 20790 points

    Keith,

    Thanks for your details about using TI processor and working environment.
    I hope you can understand "EDMA transfers" from EDMA Reference Guide.
    You can see different EDMA transfers in the section "Transfer Examples" and "Subframe Extraction Example".

  • 0 in reply to Pubesh
    Prodigy 50 points

     

    Pubesh,

    Thank you for your response.

    Is there some way to configure the EDMAs and Parameter RAM so that the transfer of data would "Ping-Pong" between 2 sets of Parameter RAM and keep the address increments (or decrements) and thus accomplish my goal ?  Is there some means of using the alternate transfer complete code (ATCC) to enable a different set of Parameter RAM for EXT_INT7 for alternating blocks or frames of data ?

    I think that I understand the EDMA Reference Guide.  It appears to me that the 2 sections that you refer to in the EDMA Reference Guide seem to focus on post acquisition data movement which is something we prefer to avoid so that the processor does not spend time on data movement and thus the processor can do more image processing. 

    I think that I understand the "EDMA transfers" in the EDMA Reference Guide.  However, the basis for my asking for help is to learn with more certainty whether or not my understanding is thorough enough to say that my goal of separating interlaced data is possible or impossible with "EDMA transfers."  Since I am new to this device, I wonder if there is some feature that I do not understand thoroughly enough to take full advantage of the "EDMA transfers" and accomplish my goal. 

    I have been told that in the past TI Application Engineers have helped the software engineers here at my employer understand the features of EDMAs more thoroughly and accomplish EDMA transfers that the software engineers thought to be impossible.  It would be helpful if I knew with more certainty whether or not my goal was possible to achieve or not.

    So my basic question remains.  Is it possible or impossible to separate interlaced image data as described previously?

    Thank you,

    Keith

  • 0 in reply to Keith Nusekabel
    TI__Mastermind 20790 points

    Keith,

    Please kindly refer the below sections in spru234 for EDMA.
    4.2 Parameter RAM (PaRAM)
    4.3.1 Alternate Transfer Chaining

    Alternate transfer chaining allows one channel to trigger another channel once for each transfer request it makes
    (once per sync event received), rather than only once per block.

    Refer the Table 4-2. EDMA Channel Parameter Descriptions-C64x DSP.

  • 0 in reply to Keith Nusekabel
    TI__Guru* 84110 points

    Keith,

    EDMA can separate the lines as you want them to be done.

    If you have interlaced video coming in to the DM643, then all the even lines will come in first and then the odd lines will come in after that. The normal drivers might be designed to merge the two sets, so you would only need to modify the drivers so the EDMA transfers copy all of the first half to one buffer and all of the second half to a second buffer.

    Does that sound like something you can implement from the example drivers you have for the DM643?

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 50 points

    Randy,

    Thank you for your response and input.

    I think that you have misunderstood the format of the data that I am receiving.  The data that I will be receiving is alternate lines of odd and even data.  The even line data will not be first and it will not be followed by the odd line data.  The data the I will be receiving is the result of interlaced image data.  I will be receiving one line of odd data followed by one line of even data, and then repeating until the full image is received.    I am trying to use the EDMAs to un-interlace the data that I am receiving.  The scenario that you described is more like the inverse of my goal.

    It seems to me that I must have one interrupt for the odd lines of data and a separate interrupt for the even lines of data in order for the EDMAs to automatically separate interlaced image data.  Do you believe this statement to be correct ?

    Some of the hardware engineers at my employer believe that this un-interlacing process can be accomplished by the EDMAs automatically, but I cannot envision how.  I believe that I have detailed the issues that I see in previous posts to this thread.

    Please let me know if more information is needed regarding this issue.

    Thank you,

    Keith

  • 0 in reply to Keith Nusekabel
    TI__Guru 63205 points

    Perhaps an illustration might help in conveying what you desire.  I realize this may be a little work to put together, but we appear to be getting hung up on terminology and lack an understanding of the data stream coming into the device.

  • 0 in reply to BrandonAzbell
    TI__Guru* 84110 points

    Brandon is correct. Interlaced video has even-even-even for a half-frame and then odd-odd-odd for a half-frame, such as for 480i or 1080i. Progressive video has even-odd-even-odd for a full frame, such as 480p, 720p, or 1080p.

    You can do what you want with EDMA. Please look at some of the examples and discussions on the TI Wiki Pages for video, and there may be some pictures to help you.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 50 points

    Brandon and Randy,

    Thank you for your input.  I must apologize for using the incorrect terminology. The input that I will be receiving is very similar to progressive video (Thank you Randy for helping to clarify this description.).  My goal then is to convert this progressive video type input into an interlaced video type output stored in RAM.  The goal is to use only EDMA channels to complete this conversion.

    I have taken a brief look at the TI Wiki Pages for video, and it appears that one of the Video Ports of the DSP is normally used for managing interlaced and progressive video images.  Unfortunately, I am working with a legacy hardware design and the Video Ports are not available to do this conversion.  I will continue to search and examine the TI Wiki Pages, but my initial searches are not encouraging.

    Thank you for the input.

    Keith

  • 0 in reply to Keith Nusekabel
    TI__Guru* 84110 points

    Keith,

    TI provides FVID drivers for the DM64x family. You will want to get these drivers, available as source code, and study the driver code and the EDMA User's Guide to learn how to write your special driver.

    The video port is not necessary, it just supplies data in lines. You can adapt the supplied drivers with your gained understanding of the EDMA and your goals for the data reconstruction.

    Regards,
    RandyP