AM335x pin mux power confict

yoniw

Hello

Is below IO power violation acceptable ?

I'm using 8bit data width 1.8v NAND flash, the selected IO set is 50 and after de selecting unused signals interface include

csn0,advn_ale,oen_ren,wen,beon_ale and 8bit data powered from VDDSHV1=1.8V and wait0 (gpio0(30) powered from VDDSHV3=3.3V

I used a 1.8v to 3.3V level shifter for wait0 signal is this acceptable ?

Yoni

over 12 years ago

0 Biser Gatchev-XID over 12 years ago

TI__Guru**** 393215 points

Hi Yoni,

The WAIT signal is an open-drain output from the NAND Flash. It's enough to place a pullup resistor to VDDSHV3 on this line.

0 yoniw over 12 years ago

Prodigy 230 points

Hi Biser

So , my pin mux selection is OK although I'm getting IO power violation indication ( GPMC brown cell ) due to wait0?

Also, will replace level shifter with a pull-up in next board spin per your suggestion

Yoni W

0 Biser Gatchev-XID over 12 years ago in reply to yoniw

TI__Guru**** 393215 points

I think so. Just in case check your NAND datasheet to confirm that WAIT is really an open-drain output from the NAND.

0 yoniw over 12 years ago in reply to Biser Gatchev-XID

Prodigy 230 points

Biser

Verified NAND wait signal is OD, it is MT29F2G08ABBEAH4-IT

Just for better understanding, looks like any pin mux power violation can be solved using external level shifters, or the AM335X has additional internal limitation ?

Yoni W

0 Biser Gatchev-XID over 12 years ago in reply to yoniw

TI__Guru**** 393215 points

Hi Yoni,

In your case the power violation can be ignored. In other cases you must take into acoount eventual delays that the level shifters will introduce. Each case must be assessed individually.

In all cases it's important that you use one of the available pinmux I/O sets (or a subset of an available I/O set). These have been validated and confirmed.

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AM335x pin mux power confict