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C6000 DDR3 routing reference plane

Feng Yan
Prodigy 30 points

Hi ，

I feel uncertain about the reference plane of signals.

As mentioned in document  《DDR3 Design Guide for Key Stone Devices》:

“Where the address and control lines are better referenced to a power or ground plane (solid), the data lines must be referenced to a solid ground plane.”

If  the data lines are routed inner, which sandwiched between power plane and ground plane, that is a strip-line structure and that means the data lines have two reference planes, power plane and ground plane.

thus, how can i guarantee  “the data lines must be referenced to a solid ground plane"?

Thank you！

 

  • 0
    TI__Mastermind 42545 points

    Hi,

    As long as you have a solid ground plane on one of the layers adjacent to the DDR3 routing you have fulfilled the requirement. Let me add one clarification to the statements above. When we state that the address and control lines can be referenced to a power plane we should clarify that the only appropriate power plane is DVDD15 and that the power plane should be continuous over the area adjacent to the DDR3 routing. The signal routing should never cross a break in either the DVDD15 plane or the ground plane. 

    Regards, Bill

  • 0 in reply to Bill Taboada
    Prodigy 30 points

    Hi Bill,

    Thank you for your kind reply.

    I still feel a bit puzzled by the point of “the data lines must be referenced to a solid ground plane”.

    There are two reference planes on the layers adjacent to DDR3 routing , one is ground plane and the other is power plane.

    As you replied, “As long as you have a solid ground plane on one of the layers adjacent to the DDR3 routing you have fulfilled the requirement.”,

    But how can I know that data lines must be referenced to the ground  plane instead of the power plane since the power plane is also the layer adjacent to the DDR3 data lines routing?


    Best regards

  • 0 in reply to Feng Yan
    TI__Mastermind 42545 points

    Hi,

    Remember that for high speed signals the return current follows the path of least inductance. Return currents traveling along a power plane will eventually have to pass through a decoupling capacitor to cross from the power plane to the ground return of the driver. Since capacitors have some inductance at higher frequencies the ground plane will be the lower impedance path. There is a good article on this at the following address. 

    http://www.icd.com.au/articles/Dumping_Ground_PCB-Aug2011.pdf

    Regards, Bill

  • 0 in reply to Bill Taboada
    Prodigy 30 points

    Hi,

    Thanks for your reply,I see what you mean!

    Best Regards