Hi,
I'm having a problem detecting "real" end of transfer with McSPI module.
The module configured as follows:
- Multichannel operation (only one channel used)
- No DMA
- No Interrupts
- TX and RX FIFO enabled
Use case:
I want to send 16Bit words in different quantities (always less than the FIFO can handle) like this:
HWREG(SOC_SPI_1_REGS+MCSPI_TX(0))=Data1;
HWREG(SOC_SPI_1_REGS+MCSPI_TX(0))=Data2;
HWREG(SOC_SPI_1_REGS+MCSPI_TX(0))=Data3;
Now I need to wait until the whole transfer is finished (CS# positive edge of last transfer is done).
First try was using TXFFE bit in SPI channel status register to check if the FIFO is empty. After this I would wait until EOT in the same register is set. Unfortunately this does not work.
Can someone from TI explain in detail when the TXFFE, TXFFF, RXFFE und RXFFF bits gets set/cleared while using FIFO buffer?
Do this flags also rely on the settings in MCSPI_XFERLEVEL register? If so does the TXFFE bit reflect an almost empty state or a real empty state of the TX FIFO?
How do the flags act when MCSPI_XFERLEVEL settings are all 0.
Thanks.
Best regards,
Patrick