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Caching DDR3 Buffer in L1D

Saravanan Kamal
Prodigy 65 points
Other Parts Discussed in Thread: TMS320C6670

Hi,

I am working on C6670 processor. In my application there is a buffer of size around 250 KB which currently resides in L2SRAM.

For utilizing L2SRAM memory, I moved this buffer to DDR3 memory location. But my requirement is to CACHE this buffer

in L1D for improving the real-time performance. But I am unable to cache this buffer in L1D.

Checked the platform.xdc file, i am restricted to use Code, Data & Stack memory sections as L2SRAM.

Is there any method to cache DDR3 in L1D ? Currently I am blocked with this issue, which is affecting the application performance.

Regards,

Saravanan.

  • 0
    TI__Mastermind 30825 points

    When the cache memory (L1D and L2 Memory's configured as cache) are configured using their Memory Attribute Registers (MARs) to cache a memory space such as DDR3's memory space (which by default is set cacheable) then when the CorePac's access the the memories, they are cached into the cache space.

    I'd recommend reading the C66x DSP Cache User Guide which can be found on the TMS320C6670 <- Product Page.

    Best Regards,
    Chad