ASSIGNING OF MAC ADDRESS FOR CORE

Hi Avinash,

I will explain MAC address topics below.  Regarding the IP layer, it depends on how to implement TCP/IP stack.  Usually, one MAC address corresponds to one IP address, so if we assign different MAC addresses to different cores, IP address should be okay.

In KeyStone architecture (includes C6678), roughly speaking, we have two methods to handle multiple MAC addresses and two EMAC ports.

In any cases, we need understanding of Multicore Navigator (Queue Manager Sub-System, or QMSS).

One method is, to tell Ethernet Switch subsystem to associate two Ethernet ports to different QMSS queues.  In short, associate the port 1 to the QMSS queue A and port 2 to queue B.  By the configuration, hardware automatically forwards a packet received at port 1 to queue A and port 2 to queue B.  After that, we design software for two cores that core 0 pops a packet from queue A and core 1 pops from queue B.  By this way, core 0 can occupy port 1 and core 1 does port 2 regardless destination MAC addresses in the packet header.

Another method is, to program PA (Packet Accelerator).  PA runs firmware (TI provides it) and the firmware routes any packets by looking into MAC, IP, TCP, and UDP header information.  We can program PA to route a different MAC address packet to a different QMSS queue.  It is as same that a core pops a packet from a specific queue to differentiate MAC addresses as mentioned above.

If the former method works for your application and you don't need PA for optimized performance, it should be easier than the latter method.  The latter method requires understanding of PA but we can have flexible configuration and also load-balance among cores and PA.

In both cases, we need to consider TCP/IP stack aspect separately if you need.

I hope it helps.

Regards,
Atsushi

Hi Atsushi,

                    Thanks for the reply. I have made certain changes in the code I can able assign single MAC Address and Single IP address and I can able to make the Mirror concept. can you just provide source code or idea regarding where and in which file the changes has to be done.  

Regards,

Avinash

Hi Avinash,

Unfortunately I didn't find the exact sample code which you wanted in MCSDK release, but PA example may be a good starting point.  You can find the sample code in pdk_C6678_1_1_2_5/packages/ti/drv/pa/example/emacExample in MCSDK.  (The numbers depend on MCSDK version.)

Originally, the code configure PA to receive any packets from GbE switch.  In the Pa_create() in painit.c (this is source code of the prebuilt library), we see the following code.

    passRegs->STREAMSWITCH.STREAMSWITCH_SOFT_RESET = (PAFRM_DEST_PDSP0 << CSL_PA_SS_STREAMSWITCH_SOFT_RESET_TXSTA_SHIFT) |
                                                     (PAFRM_DEST_PDSP0 << CSL_PA_SS_STREAMSWITCH_SOFT_RESET_TXSTB_SHIFT);

This tells Ethernet Switch (exactly Packet Streaming Interface) to route any packets to PA (Packet Accelerator).  As you seen 3.1.2 CPSW Configuration Register (CPSW_CFG_REG) in the SPRUGZ6, by default, they are directed to Packet DMA channel 22 and 23 respectively.  So if we reconfigure the register (or comment out the above code and recompile the PA library) to default, Ethernet Switch to route packets received at port 1 to DMA channel 22 and port 2 to channel 23.

After the modification, we need to configure DMA channel 22 and 23, and Rx flow 22 and 23 appropriately.  In addition, we need to write a code to receive packets from the queues.

First, I will show a sample code to configure DMA channel 23.  You need to setup channel 22 too by a similar way.  (I'm afraid that this is a sample code.  We don't support this.)

    // Rx Channel Global Config Register A
    // Registers are located at 0x0200_4800
#define RX_DESTQ            4
#define RX_FDQ              3
#define RX_PORTA 22     // No connector connected on EVM
#define RX_PORTB 23     // RJ-45 on EVM

    // Rx Channel 23
    *(int*) (0x02004800 + RX_PORTB * 32 + 0) =
            1   << 31       // Rx enable: 1
          | 0   << 30       // Rx teardown (no)
          | 0;              // Rx pause

    // Refer 4.2.4 Rx DMA Flow Configuration Region of the SPRUGR9E.
    // Rx Flow Config Register A
    // Registers are located at 0x0200_5000

    // Flow 23
    *(int*) (0x02005000 + RX_PORTB * 32 + 0) =
            0   << 30       // Rx EINFO Present (0: no)
          | 0   << 29       // Rx PSINFO Present (0: no)
          | 0   << 28       // Rx Error Handling
          | 0   << 26       // Rx Desc. Type (0: host)
          | 0   << 25       // Rx PS Location
          | 0   << 16       // Rx SOP Offset
          | 0   << 12       // Rx Dest QMGR
          | RX_DESTQ;       // Rx Dest QNUM

    *(int*) (0x02005000 + RX_PORTB * 32 + 4) =
            0x00    << 24   // RX_SRC_TAG_HI
          | 0x00    << 16   // RX_SRC_TAG_LO
          | 0x00    << 8    // RX_DST_TAG_HI
          | 0x00    << 0;   // RX_DST_TAG_LO

    *(int*) (0x02005000 + RX_PORTB * 32 + 8) =
            4   << 28       // RX_SRC_TAG_HI_SEL (4: src_tag from app)
          | 4   << 24       // RX_SRC_TAG_LO_SEL (4: src_tag from app)
          | 4   << 20       // RX_DST_TAG_HI_SEL (4: src_tag from app)
          | 4   << 16       // RX_DST_TAG_LO_SEL (4: src_tag from app)
          | 0;              // RX_SIZE_THRESH_EN (0: Don't use threshold)

    *(int*) (0x02005000 + RX_PORTB * 32 + 12) =
            0   << 28       // Rx FDQ0 SZ0 QMGR
          | RX_FDQ  << 16   // Rx FDQ0 SZ0 QNUM
          | 0;

    *(int*) (0x02005000 + RX_PORTB * 32 + 16) =
            0;

    *(int*) (0x02005000 + RX_PORTB * 32 + 20) =
            0;

    *(int*) (0x02005000 + RX_PORTB * 32 + 24) =
            0;

    *(int*) (0x02005000 + RX_PORTB * 32 + 28) =
            0;

In addition, we need to write a code to pop the queues.  I think we need to be familiar with the emacExample code to realize it...

Regards,
Atsushi