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OMAP-L138 - timing model for DDR interface

Milan Zelenka
Intellectual 870 points
Other Parts Discussed in Thread: OMAP-L138, OMAPL138

Hello,
where can I get a timing model (verilog) for the OMAP-L138 DDR controller?

Many thanks,
Milan

 

  • 0
    TI__Mastermind 35645 points

    Hi Milan,

    Thanks for your post.

    Could you please provide more details on your query posted above. Like, do you need any hardware interface level timing model for DDR controller or just timing specifications of DDR controller? If any hardware level timing model, i have to check with hardware (ASIC) folks to address your query promptly.

    But anyway, there are guidelines for using the DDR2/mDDR timing specification (SPRAAV0) which is referred in Section 5.11.3 and interface level schematics also shown in the OMAPL138 datasheet as given below:  (please refer SPRAAV0 in the datasheet below)

    http://www.ti.com/lit/ds/symlink/omap-l138.pdf

    Please also refer Section 15.2.6 (DDR2 memory controller interface) in the TRM as below:

    http://www.ti.com/lit/spruh77

    Thanks & regards,

    Sivaraj K

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  • 0 in reply to Sivaraj Kuppuraj
    Intellectual 870 points

    Hello Sivaraj,
    In order to perform timing analysis, Hyperlynx DDR wizard needs to know accurate timing for both controller and DDR memory. That's where my question comes from.

    For further details, please refer to HYP 8.2.1. manual, Chapter 17, Simulating DDRx Memory Interfaces.

    Let me know should you not be familiar with Hyperlynx.

    Thanks,
    Milan

  • 0 in reply to Milan Zelenka
    TI__Mastermind 35645 points

    Hi Milan,

    Actually, i am not familiar with Hyperlynx, but i understood that, it is a design simulation tool where signal integrity and timing analysis, PCB design pre and post layout analysis etc shall be performed. But, i think, hardware folks would be better to address your query since they would have used this simulation tool for signal integrity.

    So, Let me take care to reassign this query to hardware expert, sothat, your query will be replied soon in the same thread.

    Thanks for your response.

    Regards,

    Sivaraj K

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  • 0 in reply to Sivaraj Kuppuraj
    Intellectual 870 points

    Hello,
    may I ask for an update?

    Many thanks,
    Milan

  • 0 in reply to Milan Zelenka
    TI__Mastermind 35645 points

    Hi Milan,

    It is in the process of reassigning this post to hardware folks.

    You will get reply very soon.

    Regards,

    Sivaraj K

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    Please click the     Verify Answer button on this post if it answers your question.
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  • 0 in reply to Sivaraj Kuppuraj
    TI__Guru* 83965 points

    Hi Milan

    We worked with the field team supporting you to provide an updated IBIS model that fixes the issues input thresholds and cap values for DDR. Hopefully you have those now. Beyond that we are not tracking any additional deliverable on this. Apart from the DDR specification as part of the datasheet, the mDDR/DDR2 controller chapter and the IBIS models (primarily intended for Signal Integrity analysis), there is no other collateral that is offered for mDDR/DDR2 on this device.

    Regards

    Mukul

  • 0 in reply to Mukul Bhatnagar
    Intellectual 870 points

    Hi Mukul,
    The aim of my question was to get a Verilog timing required by HYP timing wizard.

    From your message I take it there is none available.  That's okay. I will not push.

    Thanks for your feedback.

    Best,
    Milan