HI
I am working on porting mipi dsi Lcd panel (video mode) with pandaboard ES Rev B2 , os is android 4.2.1 with kernel version 3.0.8
my panel spec is LCD size 1080x1920, HSA = 12 , HFP=18 ,HBP=19, VSA = 4 , VFP=36 ,VBP=32 , Frame rate = 60.03Hz
our setting in board-omap4panda.c below. I can't see any frame in panel , no pixel data in data lane and clk lan .
Error Msg in Consol :
[ 4.610626] OMAPFB: fb_infos allocated
[ 4.610656] OMAPFB: allocating 16777216 bytes for fb 0
[ 4.637512] smsc95xx v1.0.4
[ 4.717285] smsc95xx 1-1.1:1.0: eth0: register 'smsc95xx' at usb-ehci-omap.0-1.1, smsc95xx USB 2.0 Ethernet, 32:58:13:4b:97:fc
[ 5.032653] OMAPFB: allocated VRAM paddr af000000, vaddr f2000000
[ 5.041320] (stk) :ldisc installation timeout
[ 5.046356] (stk) :ldisc_install = 0
[ 5.051055] OMAPFB: region0 phys af000000 virt f2000000 size=16777216
[ 5.059448] OMAPFB: region1 phys 00000000 virt (null) size=0
[ 5.066253] OMAPFB: fbmems allocated
[ 5.076934] OMAPFB: check_fb_var 0
[ 5.081054] OMAPFB: max frame size 16777216, line size 7680
[ 5.087371] OMAPFB: xres = 1920, yres = 1080, vxres = 1920, vyres = 1080
[ 5.095092] OMAPFB: set_fb_fix
[ 5.095153] OMAPFB: fb_infos initialized
[ 5.103546] OMAPFB: framebuffers registered
[ 5.108520] OMAPFB: apply_changes, fb 0, ovl 0
[ 5.113586] OMAPFB: setup_overlay 0, posx 0, posy 0, outw 1920, outh 1080
[ 5.121429] OMAPFB: paddr af000000, vaddr f2000000
[ 5.126861] OMAPFB: apply_changes, fb 1, ovl 1
[ 5.132263] OMAPFB: create_framebuffers done
[ 5.140411] cannot apply mgr(lcd) on inactive device
[ 5.146118] omapfb omapfb: failed to apply dispc config
[ 5.155212] cannot apply mgr(tv) on inactive device
[ 5.160827] omapfb omapfb: failed to apply dispc config
[ 5.169891] cannot apply mgr(lcd2) on inactive device
[ 5.175659] omapfb omapfb: failed to apply dispc config
[ 5.181793] OMAPFB: mgr->apply'ed
[ 5.341583] omapdss DSI error: DSI CIO error, cio irqstatus c00000
[ 5.348724] DSI CIO IRQ 0xc00000: ERRCONTENTIONLP0_2 ERRCONTENTIONLP1_2
[ 5.360626] omapdss DSI error: DSI error, irqstatus 40010
[ 5.360687] DSI IRQ: 0x40010: WAKEUP SYNC_LOST
[ 5.372924] omapdss DISPC error: SYNC_LOST, disabling LCD
[ 5.379028] omapdss DISPC error: First SYNC_LOST.. ignoring
[ 5.385437] OMAPFB: create sysfs for fbs
[ 5.385498] OMAPFB: create sysfs for fbs
[ 5.395202] regulator_init_complete: VANA: incomplete constraints, leaving on
[ 5.404418] regulator_init_complete: VDAC: incomplete constraints, leaving on
[ 5.413452] drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
[ 5.421844] Freeing init memory: 252K
static struct omap_dss_device omap4_panda_lcd_device = {
.name = "lcd",
.driver_name = "xxx_panel",
.type = OMAP_DISPLAY_TYPE_DSI,
.data = &xxx_panel_dsi1,
.phy.dsi = {
/* Four data lanes and one clock lane used */
.clk_lane = 1,
.clk_pol = 0,
.data1_lane = 2,
.data1_pol = 0,
.data2_lane = 3,
.data2_pol = 0,
.data3_lane = 4,
.data3_pol = 0,
.data4_lane = 5,
.data4_pol = 0,
.type = OMAP_DSS_DSI_TYPE_VIDEO_MODE,
},
.clocks = {
.dispc = {
.channel = {
.lck_div = 1, /* Logic Clock = MHz */
.pck_div = 3, /* Pixel Clock = MHz */
.lcd_clk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
},
.dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK,
},
.dsi = {
.regn = 31, /*Fint = 1.2*/
.regm = 675, /*DDR Clock = 405 MHz Target,*/
.regm_dispc = 3,
.regm_dsi = 4,
.lp_clk_div = 6, /* LP Clock = MHz */
.dsi_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
},
},
.ctrl = {
.pixel_size = 24,
},
.panel.dsi_mode = OMAP_DSS_DSI_TYPE_VIDEO_MODE,
.channel = OMAP_DSS_CHANNEL_LCD,
};
static struct omap_video_timings xxx_timings = {
.x_res = 1920,
.y_res = 1080,
.pixel_clock = 135000,
.hfp = 18,
.hsw = 12,
.hbp = 19,
.vfp = 36,
.vsw = 4,
.vbp = 32,
};
REG DUMP
- DSS -
dpll4_ck 1536000000
DSS_FCK (DSS_FCLK) = 1536000000 / 9 = 170666666
- DISPC -
dispc fclk source = DSS_FCK (DSS_FCLK)
fck 170666666
- DISPC-CORE-CLK -
lck 170666666 lck div 1
- LCD1 -
lcd1_clk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
lck 557419050 lck div 1
pck 185806350 pck div 3
- LCD2 -
lcd2_clk source = DSS_FCK (DSS_FCLK)
lck 42666666 lck div 4
pck 42666666 pck div 1
- DSI1 PLL -
dsi pll source = dss_sys_clk
Fint 1238709 regn 31
CLKIN4DDR 1672257150 regm 675
DSS_FCK (DSS_FCLK) 557419050 regm_dispc 3 (off)
DSI_PLL_HSDIV_DSI (PLL1_CLK2) 418064287 regm_dsi 4 (on)
- DSI1 -
dsi fclk source = DSI_PLL_HSDIV_DSI (PLL1_CLK2)
DSI_FCLK 418064287
DDR_CLK 418064287
TxByteClkHS 104516071
LP_CLK 34838690
DISPC_REVISION 00000040
DISPC_SYSCONFIG 00002015
DISPC_SYSSTATUS 00000001
DISPC_IRQSTATUS 000000a0
DISPC_IRQENABLE 0016d64e
DISPC_CONTROL 00000329
DISPC_CONFIG 00020004
DISPC_CAPABLE 00000000
DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT) 00000000
DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT) 00000000
DISPC_LINE_STATUS 000002b0
DISPC_LINE_NUMBER 00000000
DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD) 0120110b
DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD) 02002403
DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD) 00010003
DISPC_GLOBAL_ALPHA ffffffff
DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT) 00000000
DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD) 0437077f
DISPC_CONTROL2 00000000
DISPC_CONFIG2 00000000
DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD2) 00040001
DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_OVL_BA0(OMAP_DSS_GFX) 7e000000
DISPC_OVL_BA1(OMAP_DSS_GFX) 7e000000
DISPC_OVL_POSITION(OMAP_DSS_GFX) 00000000
DISPC_OVL_SIZE(OMAP_DSS_GFX) 0437077f
DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX) 12000099
DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX) 04ff05dc
DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX) 00000500
DISPC_OVL_ROW_INC(OMAP_DSS_GFX) 00000001
DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX) 00000001
DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX) 00000000
DISPC_OVL_TABLE_BA(OMAP_DSS_GFX) 00000000
DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_OVL_PRELOAD(OMAP_DSS_GFX) 000004ff
DISPC_OVL_BA0(o) 00000000
DISPC_OVL_BA1(o) 00000000
DISPC_OVL_POSITION(o) 00000000
DISPC_OVL_SIZE(o) 00000000
DISPC_OVL_ATTRIBUTES(o) 00008400
DISPC_OVL_FIFO_THRESHOLD(o) 07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(o) 00000800
DISPC_OVL_ROW_INC(o) 00000001
DISPC_OVL_PIXEL_INC(o) 00000001
DISPC_OVL_FIR(o) 04000400
DISPC_OVL_PICTURE_SIZE(o) 00000000
DISPC_OVL_ACCU0(o) 00000000
DISPC_OVL_ACCU1(o) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_BA0_UV(o) 00000000
DISPC_OVL_BA1_UV(o) 00000000
DISPC_OVL_FIR2(o) 04000400
DISPC_OVL_ACCU2_0(o) 00000000
DISPC_OVL_ACCU2_1(o) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_ATTRIBUTES2(o) 00000000
DISPC_OVL_PRELOAD(o) 00000100
DISPC_OVL_BA0(o) 00000000
DISPC_OVL_BA1(o) 00000000
DISPC_OVL_POSITION(o) 00000000
DISPC_OVL_SIZE(o) 00000000
DISPC_OVL_ATTRIBUTES(o) 00008400
DISPC_OVL_FIFO_THRESHOLD(o) 07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(o) 00000800
DISPC_OVL_ROW_INC(o) 00000001
DISPC_OVL_PIXEL_INC(o) 00000001
DISPC_OVL_FIR(o) 04000400
DISPC_OVL_PICTURE_SIZE(o) 00000000
DISPC_OVL_ACCU0(o) 00000000
DISPC_OVL_ACCU1(o) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_BA0_UV(o) 00000000
DISPC_OVL_BA1_UV(o) 00000000
DISPC_OVL_FIR2(o) 04000400
DISPC_OVL_ACCU2_0(o) 00000000
DISPC_OVL_ACCU2_1(o) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_ATTRIBUTES2(o) 00000000
DISPC_OVL_PRELOAD(o) 00000100
DISPC_OVL_BA0(o) 00000000
DISPC_OVL_BA1(o) 00000000
DISPC_OVL_POSITION(o) 00000000
DISPC_OVL_SIZE(o) 00000000
DISPC_OVL_ATTRIBUTES(o) 00008400
DISPC_OVL_FIFO_THRESHOLD(o) 07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(o) 00000800
DISPC_OVL_ROW_INC(o) 00000001
DISPC_OVL_PIXEL_INC(o) 00000001
DISPC_OVL_FIR(o) 04000400
DISPC_OVL_PICTURE_SIZE(o) 00000000
DISPC_OVL_ACCU0(o) 00000000
DISPC_OVL_ACCU1(o) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_BA0_UV(o) 00000000
DISPC_OVL_BA1_UV(o) 00000000
DISPC_OVL_FIR2(o) 04000400
DISPC_OVL_ACCU2_0(o) 00000000
DISPC_OVL_ACCU2_1(o) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_ATTRIBUTES2(o) 00000000
DISPC_OVL_PRELOAD(o) 00000100
DSI_REVISION 00000030
DSI_SYSCONFIG 00000015
DSI_SYSSTATUS 00000001
DSI_IRQSTATUS 00000000
DSI_IRQENABLE 0015c000
DSI_CTRL 00faea98
DSI_COMPLEXIO_CFG1 6a054321
DSI_COMPLEXIO_IRQ_STATUS 00000000
DSI_COMPLEXIO_IRQ_ENABLE 3ff07fff
DSI_CLK_CTRL a0344006
DSI_TIMING1 7fff7fff
DSI_TIMING2 7fff7fff
DSI_VM_TIMING1 0800d00d
DSI_VM_TIMING2 04042420
DSI_VM_TIMING3 05c40438
DSI_CLK_TIMING 00002d16
DSI_TX_FIFO_VC_SIZE 13121110
DSI_RX_FIFO_VC_SIZE 13121110
DSI_COMPLEXIO_CFG2 00000000
DSI_RX_FIFO_VC_FULLNESS 00000000
DSI_VM_TIMING4 00487296
DSI_TX_FIFO_VC_EMPTINESS 00000000
DSI_VM_TIMING5 0082df3b
DSI_VM_TIMING6 7a6731d1
DSI_VM_TIMING7 0012000f
DSI_STOPCLK_TIMING 00000080
DSI_VC_CTRL(0) 20800790
DSI_VC_TE(0) 00000000
DSI_VC_LONG_PACKET_HEADER(0) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(0) 00000000
DSI_VC_SHORT_PACKET_HEADER(0) 00000000
DSI_VC_IRQSTATUS(0) 00000004
DSI_VC_IRQENABLE(0) 000000db
DSI_VC_CTRL(1) 20800f80
DSI_VC_TE(1) 00000000
DSI_VC_LONG_PACKET_HEADER(1) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(1) 00000000
DSI_VC_SHORT_PACKET_HEADER(1) 00000000
DSI_VC_IRQSTATUS(1) 00000004
DSI_VC_IRQENABLE(1) 000000db
DSI_VC_CTRL(2) 20800d80
DSI_VC_TE(2) 00000000
DSI_VC_LONG_PACKET_HEADER(2) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(2) 00000000
DSI_VC_SHORT_PACKET_HEADER(2) 00000000
DSI_VC_IRQSTATUS(2) 00000000
DSI_VC_IRQENABLE(2) 000000db
DSI_VC_CTRL(3) 20800d80
DSI_VC_TE(3) 00000000
DSI_VC_LONG_PACKET_HEADER(3) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(3) 00000000
DSI_VC_SHORT_PACKET_HEADER(3) 00000000
DSI_VC_IRQSTATUS(3) 00000000
DSI_VC_IRQENABLE(3) 000000db
DSI_DSIPHY_CFG0 204c1f3d
DSI_DSIPHY_CFG1 420b1c6d
DSI_DSIPHY_CFG2 b800001c
DSI_DSIPHY_CFG5 ff000000
DSI_PLL_CONTROL 00000000
DSI_PLL_STATUS 00000383
DSI_PLL_GO 00000000
DSI_PLL_CONFIGURATION1 0c45463d
DSI_PLL_CONFIGURATION2 00656008
thanks your support.
