About C674x McASP AFIFO

Hi g.f,

Thanks for your post.

To address your query, each serializer will have a dedicated data buffer (XRBUF) to receive data and as per your case, 4 serializers will receive data simultaneously in their XRBUF individually and it is not mandatory for the data from each serializer to go into AFIFO. AFIFO is used for some other purpose and it is treated as a block between McASP and the host/DMA controller. Please refer Section 23.2.4.4 & 23.1.4 in the C6748 TRM below:

http://www.ti.com/lit/spruh79

Basically, the McASP Audio FIFO (AFIFO) provides additional data buffering for the McASP. The time it takes the host or DMA controller to respond to DMA requests from the McASP may vary, so the additional buffering provided by the AFIFO allows greater tolerance to such variations. This is the purpose of AFIFO in the McASP module.

I hope, it clarifies your query.

Thanks & regards,

Sivaraj K

Hi Sivaraj,

Thank you so much for the reply.

I'm sorry that a question is incomprehensible.
I understand that 4 serializers will receive data simultaneously in their RBUF individually.

What I want to know is, if we enable AFIFO(Read FIFO)
I guess received data in each RBUF will go into the Read FIFO,
so in which order the data of each RBUF goes into the Read FIFO?

best regards,
g.f.

Hi g.f,

Thanks for your response.

Basically AFIFO provides additional buffering for the McASP module when it requests DMA controller for audio data transfer.

In your case, if the received data in each XRBUF send to Read FIFO, it will receive the data in FIFO order (First in First out) from 4 serializers.

Thanks & regards,