[OMAP-L137 - DMA Linux Driver] : Error interrupt raised with no active error present

Hi Vincent,

Thanks for your post.

I assume the error interrupt is based out of channel controller and not transfer controller. Because, there could be possibilities for reporting error conditions (BUSERR, MMRAERR, TRERR) on the transfer controller too. You can read the status of these error conditions from the ERRSTAT register if the error bits are enabled in the ERREN register, a bit set in the ERRSTAT will cause the error condition to interrupt the CPU (refer Section 18.2.11.2 in the TRM below)

Even though you mentioned that, error interrupt raised with no active errors present in all the error registers of EDMA3CC, you can still read the staus of EEVAL (error evaluate register) if a write of 1 to the EVAL bit in EEVAL is enabled. This triggers the pulse of the error interrupt if any pending errors are in EMR, QEMR, or CCERR. (refer Section 18.2.9.3 & 18.2.9.4 in the TRM below)

http://www.ti.com/lit/spruh92

May I know, Which error interrupt is exactly asserting in your case, Is it EDMA3_CC0_ERRINT? (you have not mentioned the exact error interrupt from the DMA driver, whether is it from the EDMA channel controller or transfer controller, please confirm?)

Thanks & regards,

Sivaraj K