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best EDMA operation mode

Christian Rückl
Intellectual 340 points
Other Parts Discussed in Thread: OMAPL138

Hi,

I have the follwing challange:

I have 3 ADC's (16 Bit parallel bus interface AD7643) connected to the EMIFA-interface of my OMAP L138 processor. I'm using the SoM from Critical Link MityDsp L138 which has already an 128 MB mDDR connected to the EMIFB. Now, I want to sample circular, every 1 us, each ADC and transfer this datas to the mDDR. The CPU, C6748, shall get after a certain time period (round about 100 us) all the sampled datas to do some filtering. One input line to the DSP is signaling that all 3 ADCs are finished with the actual conversion. The memory adresses for the ADC's are these:

ADC1: 0x6600 0001

ADC2: 0x6600 0004

ADC3: 0x6600 0010

Is there a way to configure the EDMA3 controller on my C6748 to transfer on every signal on the connected line, ADC finish, the Datas from the adresses above to a location in mDDR? If yes, can anybody help me to understand how?

 

Thanks a lot for all comments!!

Christian

  • 0
    Expert 1550 points

    Hi Christian , 

    1. Are you involving an FPGA also on EMIF [One input line to the DSP is signaling that all 3 ADCs are finished with the actual conversion] or ur using an GPIO 

    2. EDMA3 Controller will transfer data from MEM_LOC_1 to MEM_LOC_2 , so you need to ensure that when u enable the EDMA3 for transfer you 

        have the proper digitized data at the memory location you want . 

    3. SO based on you "input signal to DSP " you can start the engine and do an read from ADC memory location[SRC]  to DDR[DDR] directly.

    4. As you are making the the system as an SYNCHRONOUS you can directly read data from ADC1 - ADC3 in one go . 


    Hope this helps , else you let us know ...


    Ashish Mishra

    [Bangalore / INDIA ]  

  • 0
    TI__Mastermind 35645 points

    Hi Christian,

    Thanks for your post.

    Yes, it is possible to configure EDMA3 controller on C6748 to transfer each ADC's sampled data to mDDR. In my suggestion, you shall configure each DMA channel for each ADC's sampled data to receive appropriate events for dma data transfer to corresponding DMA channel's event queue in the EDMA3 channel controller. Sothat, each event queue associated with each DMA channel will be mapped to each ADC's sampled data.

    Basically, each channel is associated with a given event queue/transfer controller and with a given PaRAM set. A trigger event is needed to initiate a transfer. For DMA channels, a trigger event may be due to an external event, manual write to the event set register, or chained event. QDMA channels are autotriggered when a write is performed to the user-programmed trigger word. Once a trigger event is recognized, the event type/channel is queued in the appropriate EDMA3CC event queue. The assignment of each DMA/QDMA channel to event queue is programmable.

    Please refer Section 18.6 in the OMAPL138's TRM for the typical steps involved in setting up a transfer as given below:

    http://www.ti.com/lit/spruh77

    Hope this helps..

    Thanks & regards,

    Sivaraj K

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  • 0 in reply to Ashish Kumar Mishra
    Intellectual 340 points

    Thanks Ashish Mishra for your help to this issue!

    About point 1: the signal line for signaling that the conversion are finished on all 3 ADC's is connected to one GPIO (GP0[4])

    I'm not sure if I understood the manuals of the EDMA3-peripherial correct... Is it possible to increment the adress of the destination location, so that makes it possible to store there more ADC samples until the CPU is using this values?

     

    Br

    Christian