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DM8148 - Mcbsp Configuration

Other Parts Discussed in Thread: CCSTUDIO

Hi,

I'm working with DM8148 EVM. I'd like to configure the Mcbsp from the dsp.

In previous posts, it was written that "DSP can not access McBSP directly (at physical address 0x47000000), but it should go through the system MMU, which translates the physical addresses to virtual addresses" (shouldn't that be virtual address to physical address?). Therefore, the mmu is related to the Mcbsp configuration.

My questions:

1.a. If I disable the MMU, by setting MMU_CNTL to 0, will the dsp access McBSP physical address directly?

   b. If all dsp accesses go through the mmu, how can I access the physical address of the MMU registers (such as for setting MMU_CNTL to 0)?

2. a. When I try to read SRGR2 physical address (in previous posts, there was a debate whether SRGR2 physical address is 0x47000100 or 0x47000000, so I read both addresses) I encounter a strage phenomenon - the value being read and the value being displayed in CCS memory window aren't the same. Which is the correct value? Does the values CCS display are after MMU translation?

     For example:

           tempPtr = 0x47000228;

           Val = *tempPtr;                     // This give the value of  0x6C6E50CD to Val. However, CCS memory window show that  address 0x47000228 contains value of 0.

   b. Why is the value being read of SRGR2 isn't 0x2000 (the value after reset)?

Thanks,

Gilad

  • Gilad,

    Gilad Z said:

    1.a. If I disable the MMU, by setting MMU_CNTL to 0, will the dsp access McBSP physical address directly?

       b. If all dsp accesses go through the mmu, how can I access the physical address of the MMU registers (such as for setting MMU_CNTL to 0)?

    All DSP accesses to McBSP go through the system MMU. I think you can access the MMU from both DSP and Cortex-A8 ARM.

    When using the MMU on DSP, be aware about the known MMU bug (see errata)

    http://www.ti.com/lit/er/sprz343c/sprz343c.pdf

    Advisory 3.0.25 — DEMMU System MMU May Hang When Used in Table-Walk Mode

    Also I can provide you several links that might be in help:

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/142856.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/113109.aspx

    http://e2e.ti.com/support/embedded/linux/f/354/t/187599.aspx

    http://processors.wiki.ti.com/index.php/OMAP3_DSP_MMU_Configuration

    http://processors.wiki.ti.com/index.php/DSP_MMU_Faults

    Gilad Z said:
    2. a. When I try to read SRGR2 physical address (in previous posts, there was a debate whether SRGR2 physical address is 0x47000100 or 0x47000000, so I read both addresses) I encounter a strage phenomenon - the value being read and the value being displayed in CCS memory window aren't the same.

    Make sure you connect to C674x/DSP in CCStudio, not to Cortex-A8 ARM.

    BR
    Pavel