Detecting 6657 EVM (TMDS6657) with AMC to PCIe adapter using 'lspci' on Linux

Can someone please help!?

Claude,

Have you tried using our Linux MCSDK which supports the C6657 device.  The Linux MCSDK is available here: http://software-dl.ti.com/sdoemb/sdoemb_public_sw/linux_mcsdk/latest/index_FDS.html.

Regards.

Hi , 

The Linux MCSDK is to run Linux on the DSP and this is not what I want. I user the Linux Desktop SDK Because I want a standard Linux Box (Running on X86 or ARM) communicate with a DSP Board through PCIe. 

I have both a 6678EVM and a 6657EVM Board and I use a AMCtoPCIE adapter to be able to use it in a PC. I could make it work perfectly with the 6678 (after you guys gave me an update on the  SDK Software) but not with the 6657.

I cannot even list the 6657EVM as a PCI card. Maybe the problem is with the EVM Board or with the AMCtoPCIe or the DSP itself that is why I need help.

Regards, 

Claude,

If you can make 6678EVM + AMC-PCIE adaptor card perfectly with a Linux PC. Then, you need to set 6657 EVM in PCIE boot mode as you did for 6678 EVM.

Sw9 (1,2)  :  (OFF,ON)

Sw5 (1,2,3,4,5,6,7,8)  :  (ON,ON,ON,OFF,ON,ON,ON,ON) ==============> This should be ON,ON,ON,OFF,OFF,ON,ON,ON

Sw3 (1,2,3,4,5,6,7,8)  :  (OFF,ON,ON,OFF,ON,ON,ON,ON)

If still doesn't work, please try to re-program the IBL to EEPROM 0x51.

Regards, Eric

Hi, 

What you asked me to change has nothing to do with PCIe if I look at the REference Manual of the EVM. It only changed the PLL Multiplier so you asked me to changed it from 66.67 to 100.0 MHz. Are you sure it could have made a difference ? It did not change my situation anyway.

The PCIe mode is driven by SW3 (5:2) and SW5 (8:7) and I think I got them right.

As far as re-programing the IBL, you mean flashing "i2crom_0x51_c6657_le.bin" ? Can you explain the logic behind that ? I don't want to break my board.

Claude

Claude,

The PCIE boot set-up for 6678 and 6657 EVM are the same. What the switch 3-6 setting for 6678 should be reflected at 6657 sw3 and sw5.  Check below for 6678 PCIE boot case: http://processors.wiki.ti.com/index.php/TMDXEVM6678L_EVM_Hardware_Setup#Boot_Mode_Dip_Switch_Settings.

IBL is C:\ti\mcsdk_2_01_02_06\tools\program_evm\binaries\evm6657l\eeprom51.bin.

The EVM is shipped with IBL programed already, and it supports PCIE boot when switch setting is correct. If IBL is broken somehow, you need to re-program that. If you feel re-program IBL is risky, you can use JTAG emulator to debug why Linux PC doesn't see the PCIE card.

Regards, Eric

Hi Eric, 

For the dip switch I took the information from the EVM reference manual https://www.einfochips.com/TI/C6657%20Lite%20EVM_TechnicalReferenceManual.pdf 

     but there seems to be confusion between (Table 2.2 and Table 3.18, 3.19) : One says that SW5 6:4 is about PLL the other says something different 

Before I do anything to the board, I really want to make sure that my dip switches are OK, Can you tell me for sure which doc I should refer to and if you have something better (not from 6678) , let me know. 

Claude 

Claude,

Table 2.2 is correct. Table 3.18 is also correct. But Table 3.19 is wrong.

Before you flash IBL to EEPROM 0x51, can you let me know your 6657 is an alpha/beta/production card?

For alpha board: the FPGA force the boot from IBL first, if your PC can't find 6657 card in PCIE boot mode, you can update IBL.

For production board: it boot directly from BOOTROM (no IBL), so updating IBL is unnecessary. The ROM code may have some issue causing the PCIE enumeration failure when using with PC with Spread Spectrum Clock.

For Beta board, I am not sure, need to double check.

Regards, Eric

Hi Eric, 

My Board is probably a production board since I bought it recently from ti.com and it has been available for a long time. Anyway, I don't how to verify that.

So I did I you suggested nevertheless which means that I reprogrammed "eeprom51.bin" into the board and it did not fix the problem. 

Going back to Dip-Switches, you say that Table 2.2 is correct so

- I need to find the definition of SW3 (6..8) and SW5 (1..3) which are not defined in table 2.2

- What PLL Multiplier should be used for PCIe ?

Then you say that 3.18 is good but again Boot DEVICE Config is unknown ?

So Again my Config is

SW3(1,2,3,4,5,6,7,8) (OFF,ON,ON,OFF,ON,ON,ON,ON)

SW5(1,2,3,4,5,6,7,8) (ON,ON,ON,OFF,OFF,ON,ON,ON)

SW9(1,2) (OFF,ON)

Finally should I expect that lspci work in Linux ? or Should I download something else to the board to make it work (Like a PCIe bootloader). I would have hope that at least the card is detected before I can download the Boot Loader but I don't know enough to tell .

Claude 

Hi, 

Still looking for solution on that problem. Should I expect one ? or does this Eval board not supporting PCIe ?

I also tried different things like removing the XDS-200 emulation board and disabling it, without success. 

If you don't have a solution, what do you propose in order to troubleshooting it ? Use the console port ? The emulator through CCS ? Anything to look for ?

I really need to know if using 6657 with PCIe is viable solution for our next product architecture. 

Thank you

Claude,

So Again my Config is

SW3(1,2,3,4,5,6,7,8) (OFF,ON,ON,OFF,ON,ON,ON,ON)

SW5(1,2,3,4,5,6,7,8) (ON,ON,ON,OFF,OFF,ON,ON,ON)

SW9(1,2) (OFF,ON)

This is the correct setting of the PCIE boot mode. For the meaning of the pin, please check 6657 data sheet 2.5 Boot Modes Supported and PLL Settings. SW3 PIN 1 is LE/BE, starting pin 2, it maps to BOOTMODE[0:12]. E.,g, SW3, PIN 2-4 is BOOTMODE[0:2]. 

To check if your card is a production card or not: look at the 6657 EVM Technical Reference Manual, 2.3 Board Revision ID. What is your board? Also, put card in PCIE boot mode, power it on, use an emulator to connect to core 0, where is the Program Counter (PC)? If it is inside bootrom (address 0x20b0_xxxx), then it is a production card, if it is inside L2 (0x0080_xxxx), it is a alpha card.

For the production card, the bootrom code has some issue and PCIE enumeration may not work with a PC with SSC clock.

For the alpha board, we can try to help you make it work with a Linux PC.

Regards, Eric

Thank you for the answer.

I can confirm from the Program counter test that I have a production card (since PC is 0x20b010b0). 

When you say that the bootrom has some issues, does it means that they cannot be solved ? I tried the board in several Computer with different characteristics and I still have the same problem. 

Does the fact that it does not work with the EVM mean that the 6657 PCIe interface will not work when we connect it in our final design to our processor ? i.e. Is the PCIe interface on the 6657 broken/useless ?

If there are solutions (Hardware or software), I am ready to try them all since this is the only way I have to setup a development environment which is critical and so far I am blocked and think about considering another DSP.

Regard, 

Claude

Hi 

When reading  some doc of the mcsdk bootloader example (c:\ti\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\docs\README.pdf ) , I found this 

Below are the steps done in the IBL in PCIE boot mode:
• FPGA samples the boot mode pins
• FPGA forces the DSP to boot via I2C bus address 0x51
• PLL is initialized correctly by the IBL on the I2C.
• IBL reads the sampled boot mode from an FPGA register.
• IBL checks the boot mode, if it is not I2C boot or it is I2C boot but with bus address
0x50, IBL writes boot mode into the DEVSTAT register
• IBL then checks if the boot mode is PCIE boot or not. If it is, it executes some PCIE
workaround to configure the PCIE registers (mainly to accept spread spectrum clock) and
stays inside IBL by first clearing the magic address and then monitoring it for PCIE boot.

This text is about the 6678 but Is the 6657EVM capable of doing the last part which is to do the workaround that configures the PCIE registers ?

If not, is it possible to get that piece of code that does it ?

Thanks 

Claude,

In production 6678 EVM, there is some code on FPGA to re-direct the boot from bootrom to IBL, the IBL code configures the PCIE and makes the enumeration with a Linux PC (using spread spectrum clock) happening.

In production 6657 EVM, the FPGA re-direct code is removed however, and the card boot from bootrom directly and may have issue when working with a Linux PC. I knew 6657 DSP pcie interface work well with other devices (e.g, FPGA) when using narrow spectrum clock (100MHz) from several forum posts. 

To make 6657 EVM working with a PC, one approach is: the FPGA and IBL both needs to be re-programed. How to program IBL is published but not the FPGA. I am checking what the suggestion is and will get back to you.

Regards, Eric

Claude,

The older IBL with FPGA was a patch solution. Multiple changes were made to the FPGA/IBL/MCSDK while transitioning from pre-production to production.  Reverting back may uncover issues and incompatibilities. That is not a supported configuration and is not suggested. Sorry for this!

Regards, Eric

Hi Eric, 

I finally found a way to fix it. Actually, my design did not require to run a PC(x86) as a host but a i.MX6(ARM) instead.

I was using the x86 because it was more convenient for initial development. Today I connected the i.MX6 Board to the DSP EVMs and I could enumerate both the 6678 and the 6657. It is probably due to the fact the the IMX6 board does not use SSC.  

6678 enumerates as b005 and 6657 ID is b006. 

Now I just need to focus on the software part which means that I need to port the code of the Linux Desktop SDK to ARM. 

Just to make sure I am on the right track, Now that I can enumerate the 6657, Do you see any other problems on the DSP side ? to make my setup work ?

Regards

Claude

Claude,

Good to know 6657 EVM works with an ARM via PCIE interface! I don't see any other problems on DSP side.

Regards, Eric 

Thanks

One last point before closing this thread. I get these message on boot up related to pci negiciation with the 6657EVM

pci 0000:01:00.0: [104c:b006] type 0 class 0x000480
pci 0000:01:00.0: reg 10: [mem 0x00000000-0x00000fff]
pci 0000:01:00.0: reg 14: [mem 0x00000000-0x01ffffff pref]
pci 0000:01:00.0: reg 18: [mem 0x00000000-0x01ffffff pref]
pci 0000:01:00.0: reg 1c: [mem 0x00000000-0x01ffffff pref]
pci 0000:01:00.0: reg 20: [mem 0x00000000-0x01ffffff pref]
pci 0000:01:00.0: reg 24: [mem 0x00000000-0x01ffffff pref]
pci 0000:01:00.0: BAR 1: can't assign mem pref (size 0x2000000)
pci 0000:01:00.0: BAR 2: can't assign mem pref (size 0x2000000)
pci 0000:01:00.0: BAR 3: can't assign mem pref (size 0x2000000)
pci 0000:01:00.0: BAR 4: can't assign mem pref (size 0x2000000)
pci 0000:01:00.0: BAR 5: can't assign mem pref (size 0x2000000)
pci 0000:01:00.0: BAR 0: assigned [mem 0x01200000-0x01200fff]
pci 0000:01:00.0: BAR 0: set to [mem 0x01200000-0x01200fff] (PCI address [0x1200000-0x1200fff])

Do you think that there will be a problem caused by BAR 1,2,3,4,5 not properly assigned ? 

Claude

Claude,

BAR 0 is for PCIE MMR, BAR 1--5 is for memory region you can really use. From 6657 data sheet,

Table 2-12 BAR Config / PCIe Window Sizes. You can configure the BAR size requested by 6657 by switch pins. I believe you set them as 32M/32/32/32 and ARM can't grant you so many memory resource. Can you try some other combinations? E.g (0b0001 or 0b1001), if you can get 16M or 4M?

Regards, Eric

Hi Claude,

I am having the same issue, did you find a solution for " can't assign mem pref "?

I posted here: http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/335131.aspx

Thanks,

Dirk

Hi Dirk,

Our final solution was a combination of different things. 

First we cannot used the default PCIe configuration on the EVM. We need to put the EVM in EEPROM boot (a.k.a. IBL) and we used a custom IBL that configures PCIe the way we want. And I think that we also had to modified the kernel on the host side but this part may not be required (It is one of many things we tried)

Claude

Hi,

Is it possible to connect the 6657 EVM (TMDSEVM6657LS) with x86 computer via PCIE interface ? (OS : windows 7)

Thanks,

Ivgeni.

Hi Claude et al,

A belated enquiry, but you say the C6657 is supported by the Linux MCSDK?

When I  look at  supported platforms, it is not listed however.

Is it using the same image as the 6678?

Regards

Anthony

Hi Anthony,

Yes. It supports. Linux host loader should be re-build to use it.

PATH: ti\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\linux_host_loader

Please refer readme.pdf (\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\docs\Readme.pdf). 

C6657 platform supports only ddrinit/helloworld/post demos.

Are you referring Desktop Linux SDK or BIOS MCSDK? There is no Linux MCSDK for Keystone I devices.

Thanks.