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DDR3 bytewise SW leveling

ShilpaByrichetty
Intellectual 985 points

We have custom DM8148 EVM and we are trying to fine tune the DDR PHY with Byte wise SW leveling.

We are following the instructions mentioned in the link below:

http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot

Our DQS trace length for Byte 0 is greater than CK trace length and when the values are entered in the RatioSeed_TI814x.xls excel sheet, WR DQS value is negative. Attached is the file with our trace lengths.

What is the correct formula to calculate DQS when DQS trace > CK trace?

Thanks,
Shilpa.

5460.RatioSeed_TI814x.xls

  • 0
    TI__Guru**** 170625 points

    Hi Shilpa,

    This is what we have in http://processors.wiki.ti.com/index.php/AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling

    CMDx_PHY_INVERT_CLKOUT - In addition to programming these registers with 0 or 1 as defined below, plug this value into the spreadsheet to get the proper seed values for the program below.

    • If (DDR_CK length) < (DDR_DQS length), program this register to 1
    • If (DDR_CK length) > (DDR_DQS length), program this register to 0

    Even the wiki page is for AM335x device, I suspect the same is valid for DM8148 device also.

    Best regards,
    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 985 points

    Thanks Pavel. That worked.

    Shilpa.