LPDDR RAM is random wrong in AM335X, about the LPDDR configuration

The LPDDR is  ISSI IS43LR16640A-6BL;

and we follow the LPDDR Routing Guidelines, as given in the AM335X Datasheet, Rev.F, section 5.6.2.1!

Hi Biser,

Thanks, and I have attached the documents in this case.

And Additional info is: we add 33ohm serial resistor on LPDDR signal lines, will these resistors affect the register configuration? How to adjust the register setting if required?

Thank you, We have a 49.9Ohm 1% resistor to GND on DDR_VTP processor pin.

in addition, we are using AM3352ZCED50 now

Hi biser,

Sorry, I don't understand what is your means?

I have tried different configuration for the IS43LR16640A6BL_EMIF_SDCFG(that's SDRAM_CONFIG)  and  IS43LR16640A6BL_EMIF_SDREF(that's SDRAM_REF_CTRL);

but i haven't ever tried to set IS43LR16640A6BL_EMIF_SDCFG to 0x20042EA2, set IS43LR16640A6BL_EMIF_SDREF to 0x00000514;

your means is whether to let me try to set IS43LR16640A6BL_EMIF_SDREF to 0x00000514?

or other somethings?

But for IS43LR16640A6BL_EMIF_SDCFG to 0x20042EA2, I have some questions;

0x20042EA2 is 0010 0000 0000 0100 0010 1110 1010 0010, refer to the Table7-113.SDRAM_CONFIG Register Field Descriptions

1. you set 15-14 reg_narrow_mode as 0, that is to say, you Set LPDDR as 32-bit, but the datasheet of IS43LR16640A denote it's 16bits DDR.

2.you set 13-10 reg_cl as 1011(that's 11), that is too say, you Set CASLatency as 11, the AM335X data sheet say "Valueof 2and3(CAS latency of 2and3) are supported for LPDDR1", the IS43LR16640A datasheet also say it support CL 2 or 3;

It seems that the value you are setting is not supported by IS43LR16640A, is it right?

Hi biaser,

Thanks for you reply!

I have tried to set reg_sdram_drive to 1/8,1/4,1/2,FULL, and I  have tried set Freq of the LPDDR to 50M, 100M, 166M; it seems that the issue still exist.

Biser Gatchev-XID said:

Your settings are calculated for 166MHz, you shouldn't change only the frequency. As for reg_sdram_drive I thinks that only full and 1/2 should be tried.

thanks, i have tried the two settings, but it doesn't work;

By the way, when i want to change the frequency of LPDDR, i shall calculate the IS43LR16640A6BL_EMIF_SDREF again and call config_ddr(new frequency,,) in s_init.

It's not work, now;

I don't know whether the configuration of MPU shall affect it?

Maybe you know, The MAX Freq of AM3352 is 500MHZ;

I configure MPU in pll_init() in clock.c as following:

mpu_pll_config(MPUPLL_M_300);
core_pll_config(OPP_100);

and then init the LPDDR;

And any other sides(software and hardware) we can check, verify or measure to find the root cause about LPDDR doesn't work?