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SRIO port control on C6678

Brian Woolf
Prodigy 160 points

Dear Sir.

I'm trying to make a simple SRIO repeater application using 6678EVM.
You know, 6678 has 4 SRIO ports and I want to read/write to different 1x port in my application.
That is, I want send data to lane0 or lane1 separately, and vice versa for recv logic.

I read user guide and found that I should control PLM_SP(n)_PATH_CTL register or CSL_SRIO_SetPLMPortPathControlMode funciton.

At this time, my question is how can I actually direct output port in SRIO LLD level when I use Srio_sockSend or Srio_sockRecv function.
SRIO LLD contains some control functions, but I cannot find any parameter for lane port control.

Regards,
Stellar

  • 0
    TI__Mastermind 23525 points

    Are you using directIO traffic, or messaging?  I'll ask someone more familiar with the LLD to respond, but if it is directIO traffic and uses the LSU, there is a portID field in LSU_Reg4.  If you use messaging, the TX queue to output port mapping is done with the RIO_TX_QUEUE_SCH_INFOn registers.

    Regards,

    Travis

  • 0 in reply to tscheck
    Prodigy 160 points

    I use streaming (type9) data traffic in my program.

    And, I reviewed C:\ti\pdk_C6678_1_1_2_5\packages\ti\drv\srio\src\srio_drv.c code.

    For DIO, there is code for LSU_Reg4 handling in Srio_sockSend_DIO function.

    But I still cannot find code for messaging type9 packet.

    Is RIO_TX_QUEUE_SCH_INFOn register control is not included in srio_drv.c ?