Hello,
I got a problem when using the vpif interface of DM6467.
When I read the user guide of vpif 
I think it means that when I configure this bit of CH0_CTRL register as 0, the input data should be changed at the rising edge of the input clock,and , in turn , the vpif interface will capture the data at the falling edge of th input clock. And the vice versa.
But the fact is just in the opposite side.
When I control the input data being changed at the rising edge of the input clock, and configure this bit of CH0_CTRL register as 0, sometimes the vpif interface cannot receive video data properly.
If I control the input data being changed at the rising edge of the input clock, and configure this bit of CH0_CTRL register as 1, the vpif interface will receive video data properly all the time.
So I wonder if there's something wrong with the vpif datasheet or if I have a misunderstanding of it.
Is there anybody can help me ? Thank you very much!