• State Resolved
  • Locked Locked
  • Replies 11 replies
  • Subscribers 98 subscribers
  • Views 3212 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM335x-ICE EtherCAT Process data Watchdog expired

Louis chou
Intellectual 700 points


Hi,

Since I just want the Digital inputs and Digital outputs, so I modify the tiescappl.h of the 1.0.0.8 SDK.

Remove the AI and Motor Outputs and modify the XML file too.

But when I used the TwinCAT and want to active free run the "TI_ESC" device, but It always get the 0x001b value of AL status code (0x134:0x135).

TI_ESC can't change the Safe-OP to OP mode, because the Process Data Watchdog expired.

Have any suggestion?

Following is the codes.

/******************************************************************************
*                    Object 0x1C12: RxPDO assignment
******************************************************************************/
#ifdef _OBJD_
OBJCONST TSDOINFOENTRYDESC    OBJMEM asEntryDesc0x1C12[] = {
   {DEFTYPE_UNSIGNED8, 0x08, ACCESS_READ},
   {DEFTYPE_UNSIGNED16, 0x10, ACCESS_READ}};
   //{DEFTYPE_UNSIGNED16, 0x10, ACCESS_READ}};
OBJCONST UCHAR OBJMEM aName0x1C12[] = "RxPDO assign";
#endif //#ifdef _OBJD_

typedef struct STRUCT_PACKED_START {
   UINT16   u16SubIndex0;
   UINT16   aEntries[1];
} STRUCT_PACKED_END
TOBJ1C12;

PROTO TOBJ1C12 sRxPDOassign
#ifdef _TIESC_HW_
= {0x01, {0x1601}}//, 0x1602}}
#endif
;

/******************************************************************************
*                    Object 0x1C13: TxPDO assignment
******************************************************************************/
#ifdef _OBJD_
OBJCONST TSDOINFOENTRYDESC    OBJMEM asEntryDesc0x1C13[] = {
   {DEFTYPE_UNSIGNED8, 0x08, ACCESS_READ},
   {DEFTYPE_UNSIGNED16, 0x10, ACCESS_READ}};
   //{DEFTYPE_UNSIGNED16, 0x10, ACCESS_READ}};
OBJCONST UCHAR OBJMEM aName0x1C13[] = "TxPDO assign";
#endif //#ifdef _OBJD_

typedef struct STRUCT_PACKED_START {
   UINT16   u16SubIndex0;
   UINT16   aEntries[1];
} STRUCT_PACKED_END
TOBJ1C13;


PROTO TOBJ1C13 sTxPDOassign
#ifdef _TIESC_HW_
= {0x01, {0x1A00}}//, 0x1A03}}
#endif
;

#ifdef _OBJD_
/*if _PIC18 is enabled the object dictionary is fixed defined in coeappl.c*/
TOBJECT    OBJMEM ApplicationObjDic[] = {
   /* Object 0x1601 */
   {NULL,NULL,  0x1601, {DEFTYPE_PDOMAPPING, 8 | (OBJCODE_REC << 8)}, asEntryDesc0x1601, aName0x1601, &RxPDOMap, NULL, NULL, 0x0000 },
   /* Object 0x1602 */
//   {NULL,NULL,  0x1602, {DEFTYPE_PDOMAPPING, 3 | (OBJCODE_REC << 8)}, asEntryDesc0x1602, aName0x1602, &RxPDO1Map, NULL, NULL, 0x0000 },
   /* Object 0x1A00 */
   {NULL,NULL,   0x1A00, {DEFTYPE_PDOMAPPING, 8 | (OBJCODE_REC << 8)}, asEntryDesc0x1A00, aName0x1A00, &TxPDOMap, NULL, NULL, 0x0000 },
   /* Object 0x1A03 */
//   {NULL,NULL,   0x1A03, {DEFTYPE_PDOMAPPING, 2 | (OBJCODE_REC << 8)}, asEntryDesc0x1A03, aName0x1A03, &sAITxPDO1Map, NULL, NULL, 0x0000 },
    /* Object 0x1C12 */
   {NULL,NULL,   0x1C12, {DEFTYPE_UNSIGNED16, 1 | (OBJCODE_ARR << 8)}, asEntryDesc0x1C12, aName0x1C12, &sRxPDOassign, NULL, NULL, 0x0000 },
     /* Object 0x1C13 */
    {NULL,NULL,   0x1C13, {DEFTYPE_UNSIGNED16, 1 | (OBJCODE_ARR << 8)}, asEntryDesc0x1C13, aName0x1C13, &sTxPDOassign, NULL, NULL, 0x0000 },
   /* Object 0x6000 */
   {NULL,NULL,   0x6000, {DEFTYPE_RECORD, 8 | (OBJCODE_REC << 8)}, asEntryDesc0x6000, aName0x6000, &sDIInputs, NULL, NULL, 0x0000 },
   /* Object 0x6020 */
//   {NULL,NULL,   0x6030, {DEFTYPE_RECORD, 2 | (OBJCODE_REC << 8)}, asEntryDesc0x6030, aName0x6030, &sAI1Inputs, NULL, NULL, 0x0000 },
   /* Object 0x7010 */
   {NULL,NULL,   0x7010, {DEFTYPE_RECORD, 8 | (OBJCODE_REC << 8)}, asEntryDesc0x7010, aName0x7010, &sDOOutputs, NULL, NULL, 0x0000 },
   /* Object 0x7020 */
//   {NULL,NULL,   0x7020, {DEFTYPE_RECORD, 3 | (OBJCODE_REC << 8)}, asEntryDesc0x7020, aName0x7020, &sDO1Outputs, NULL, NULL, 0x0000 },
   {NULL,NULL, 0xFFFF, {0, 0}, NULL, NULL, NULL, NULL, NULL, 0x0000}};
#endif    //#ifdef _OBJD_

Best regards,

Louis chou

  • 0
    TI__Mastermind 49401 points

    Hi,

    Most likely SM2 is still configured for old length value. Did you adjust SM2 and SM3 size as well in ESI XML to reflect the above change?

    <Sm DefaultSize="5" StartAddress="#x1800" ControlByte="#x64" Enable="1">Outputs</Sm>
    <Sm DefaultSize="7" StartAddress="#x1c00" ControlByte="#x20" Enable="1">Inputs</Sm>

  • 0 in reply to PratheeshGangadhar
    Intellectual 700 points

    Yes, I have modified the ESI XML file.

    <Sm DefaultSize="1" StartAddress="#x1800" ControlByte="#x64" Enable="1">Outputs</Sm>
    <Sm DefaultSize="1" StartAddress="#x1c00" ControlByte="#x20" Enable="1">Inputs</Sm>

    And also adjust the elements of Process data object in XML file.

    Best regards,

    Louis

  • 0 in reply to Louis chou
    Intellectual 700 points

    Hi,

    Can you success modify the TI_ESC to only have 8 of digital inputs and 8 of digital outputs?

    Best regards,

    Louis

  • 0 in reply to Louis chou
    TI__Mastermind 49401 points

    Hi,

    No - we can't either. This is complying behavior to ESC register spec from Beckhoff - you can't have an SM activated if length <= 1. So you must configure minimum 2 byte length for digital I/O.

    I will clarify this in our register documentation -  I agree that WD trigger not generated when length is set to 1 is a minor variation from spec.

  • 0 in reply to PratheeshGangadhar
    Intellectual 700 points

    Hi, PratheeshGangadhar

      > I agree that WD trigger not generated when length is set to 1 is a minor variation from spec.

    I feel some doubts for this sentence, It not identical with the register description.


    1. So if I just want to have eight bits of DI and eight bits of DO, have any suggestion to implement this?

    2. Do you know why the EtherCAT spec. to define SM Length which shall be greater 1 ?


    Best regards,

    Louis

  • 0 in reply to Louis chou
    TI__Mastermind 44306 points

    Louis,

    louis chou said:

    1. So if I just want to have eight bits of DI and eight bits of DO, have any suggestion to implement this?

    Just don't use the second byte of a 16 bit transfer.

    louis chou said:

    2. Do you know why the EtherCAT spec. to define SM Length which shall be greater 1 ?

    Most likely HW related. But you better ask Beckhoff for that.

    Regards.

  • 0 in reply to Louis chou
    TI__Mastermind 49401 points

    > So if I just want to have eight bits of DI and eight bits of DO, have any suggestion to implement this?

    Add a dummy byte

    > Do you know why the EtherCAT spec. to define SM Length which shall be greater 1 ?

    Looks tied to SM implementation in Beckhoff h/w as for SM operation distinction between first byte and last byte might be necessary to lock/unlock a buffer.

  • 0 in reply to Frank Walzer
    Intellectual 700 points

    Dear Frank and PratheeshGangadhar,

              Thanks you.

    So if I used the dummy byte solution, and when I link 50 TI-ESC slaves which modify to 8 DI and 8 DO used 16 bits transfer.

    Therefore there have 100 bytes which 50 bytes is PDO and 50 bytes is dummy bytes at the data field of EtherCAT datagram ?

    Best regards,

    Louis

  • 0 in reply to Louis chou
    TI__Mastermind 49401 points

    Hi,

    Good point - still 50 bytes correspond to only 4us (overhead) w.r.t cycle time. 

    Another way is to implement 2 vendor specific registers for input and output and control them directly without using SM via LRW datagram.

    Catch is that you won't be getting any process data interrupts - so Host A8 application needs to periodically read (output) and write (input) to these registers based on application requirement.

  • 0 in reply to PratheeshGangadhar
    Intellectual 700 points

    Dear PratheeshGangadhar,

    >Good point - still 50 bytes correspond to only 4us (overhead) w.r.t cycle time.

    Can you explain more clearly, please?

    How to calculate the time to 4us?


    There is another question want to ask you.

        The AM335x-ICE guarantee the processing latency is 700ns which means that regardless of the size of the packet [64 bytes (min). or 1522 bytes (Max.)]?


    Best regards,

    Louis

  • 0 in reply to Louis chou
    TI__Mastermind 49401 points

    Hi, 

    >How to calculate the time to 4us?

    100 Mbits /s line rate => 80ns / byte. So 50 bytes equivalent to 4000ns ethernet frame time. 

    > The AM335x-ICE guarantee the processing latency is 700ns which means that regardless of the size of the packet [64 bytes (min). or 1522 bytes (Max.)]?

    Yes - 700ns (including TLK phy latency) since on the fly processing using PRU is done on 16-bit/8-bit data from MII interface - it really does not depend on packet length.

    Note that for a special scenario when multiple process data SMs (> 2 SMs) are accessed in a single datagram for a given slave this latency is high and will be < 1100ns. Such a scenario does not arise for 4SM use cases. Also for applications requiring low latency - recommendation is to multiplex all process data in to 2 process data SMs (one read, one write)