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AM3352 : how to configure RMII i/f on u-boot & kernel??

Devin Park
Expert 5965 points

 

Hi,

AM335x EVMs use only MII and RGMII and then there is no sample codes for RMII. But, I try to use two RMII PHYs and so wonder if our EZSDK supports RMII also without issue.

 below are source codes for RGMII on U-boot and Kernel.

<current SK board configuration>

                -U-boot

/* MII mode defines */

#define MII_MODE_ENABLE                      0x0

#define RGMII_MODE_ENABLE                0x3A

                                writel(RGMII_MODE_ENABLE, &cdev->miisel);

                                cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =

                                                                PHY_INTERFACE_MODE_RGMII;

                -Kernel-

am33xx_cpsw_init(AM33XX_CPSW_MODE_RGMII, NULL, NULL);

 

 

For RMII, I guess that PHY_INTERFACE_MODE_RMII & AM33XX_CPSW_MODE_RMII should be used(I could find this variables in the source codes).

However, RMII_MODE_ENABLE is not defined in board.c of U-boot. From TRM, it will be 0x3F.

9.3.31 gmii_sel Register (offset = 650h) [reset = 0h]

 

 So I wonder if these are all we have to do for RMII mode. Please confirm it.

<my modification for RMII>

                -U-boot

                                #define RMII_MODE_ENABLE 0x3f

                                writel(RMII_MODE_ENABLE, &cdev->miisel);

                                cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =

                                                                PHY_INTERFACE_MODE_RMII;

                -Kernel-

                                 <pinmux modification....>

                                 am33xx_cpsw_init(AM33XX_CPSW_MODE_RMII, NULL, NULL);

 

Thanks,

Devin

 

  • 0
    TI__Genius 15510 points

    To use RMII you must have an external clock source and make sure in the pin mux the pin is an input. The value written to gmii_sel would be 0xC5 (bits 7:6 are 1 for clock input  mode while bits 3:0 are 0101 to select RMII mode).

    Steve K.

  • 0 in reply to Steve Kipisz
    TI__Expert 5965 points

    Hi Steve,

    Thanks for your comment. You're right. The rgmii_sel is 0xC5 for RMII.

    BTW, I have one more question.

    We'll use an external osc for a RMII phy.

    Now the RMII phy needs a 25Mhz clock. I guess the phy will make a 50Mhz clock internally from the 25Mhz clock.

    Is there no issue although we use the PHY with 25Mhz?

    Thanks,

    Devin

     

  • 0 in reply to Devin Park
    TI__Guru 62945 points

    Some RMII PHYs may allow you to connect a 25MHz crystal to an internal oscillator and the PHY will source the required 50MHz RMII Reference Clock to AM335x.

    Some RMII PHYs may require you to source a 50MHz Reference Clock from an external LVCMOS clock source.  In this case the same clock source normally sources the 50MHz RMII Reference Clock to AM335x.

    Some RMII PHYs may support both options based on the PHY configuration.

    You need to determine the clocking method supported by the PHY you have chosen and connect it per this requirement.

    Regards,
    Paul