AM335x basic GPMC configuration

Kurtis Unger said:

For example, how do we map the address space?  In http://e2e.ti.com/support/arm/sitara_arm/f/791/t/252864.aspx there are mention of default BASEADDRESSes, where are they listed?

First, note that according to Section 2 "Memory Map" in the TRM that the GPMC occupies the first 512 MB of space of the AM335x memory map (with the exception of the 1st MB).  So any CPU accesses to physical addresses less than 0x20000000 will be routed to the GPMC.  The GPMC has 8 different chip selects which can be connected to external devices.  So now you must program the GPMC in order for it to know how to divide that 512MB of space among all the available chip selects.  So, for each chip select you must specify a base address and size.

The size is selected by the "MASKADDRESS" field of GPMC_CONFIG7_i.  The base address is configured by BASEADDRESS.  The thing to note is that you are specifying bits 29:24 of the address (where bit 0 is the LSB).  Essentially your taking the most significant byte of the intended physical address...  So let's say we want to make the following mapping:

CS0 -> Size 16MB, Base address 0x0100_0000

CS1 -> Size 64MB, Base address 0x0400_0000

Now first thing to note is that there is a "hole" between CS0 and CS1, but that was required in order to have the proper alignment of CS1, i.e. since we have a 64MB size we must be aligned to a 64MB boundary.  Also, I avoided address 0 since the first MB is inaccessible as noted in Section 2.

To program this configuration we would do:

GPMC_CONFIG7_0

• MASKADDRESS = 0xF
• BASEADDRESS = 1

GPMC_CONFIG7_1

• MASKADDRESS = 0xC
• BASEADDRESS = 4

The "default" addresses were just referring to the hardware defaults (i.e. the register was not programmed since the chip select was not being used).  The "defaults" are shown for all registers in the TRM.  When below a given bit-field it says something like "R/W-0" that means the field is readable, writable, and has a default value (after reset) of 0.

Hi Brad,

  Thanks for that fairly clear example, that's similar to what we've done.  Unfortunately we're still not seeing the results we expect.

Specifically, we use the following command to set up CS1 (GPMC_CONFIG7_1) to MASKADDRESS = 0xF, BASEADDRESS = 4:

devmem2 0x500000A8 w 0x00000F04

After this we attempt to toggle (enable) the CS1 line with:

devmem2 0x500000A8 w 0x00000F44

But the line stays high (disabled).  What are we missing?  Will that line only toggle when that memory space (0x04000...) is addressed?  Are we even able to manually toggle the CS1 line or is this all controlled transparently by the GPMC when we access that memory space?

Cheers,

Kurtis

To follow up and somewhat answer my own question...

We had an error in our set up and the lines are behaving as expected.  The CS1 goes low when we enable it and then access that memory space.

I'm sure we'll have other hurdles but this one is cleared.  Thanks

So about that next hurdle...

As I scope the A0 and A1 lines (balls R1 & R2 on the ZCZ package) I expect that they would increment as I read from memory using

devmem2 0x04000000 <- A0 & A1 low

devmem2 0x04000001 <- A0 high, A1 low

devmem2 0x04000002 <- A0 low, A1 high,

etc...

but I don't see that at all.  There is some signaling on those lines but it does not change as I increment the address space.

Thanks in advance...

The mapping of addresses to pins is given in Table 7-5 GPMC Pin Multiplexing Options.  Do you have the memory setup as a 16-bit interface?  If so, A0 is not used...

As far as I know we have set it to 8 bit mapping, ie we set bits 13-12 on GPMC_CONFIG1_1 to 00

That did it! 

Thanks for the insights and the very quick replies!

Hi Brad,

We are using the same configuration and device size is 16 bit. We are using ccs6.1 in a non os platform.

So after initilization if i want to read from GPMC memory, will  the following code works?

uint16_t ret ;

ret =  (*(volatile uint16_t*) 0x00400002);  

Regards,

Jinu