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Keystone II - confirmation of multiplexed pins?

AnBer
Mastermind 30110 points

Team,

Could you please confirm that on Keystone II the only multiplexed pins are the GPIO (that can be used as interrupt source, EDMA trigger or GPIO)?
The only mention I found about about muxed pins was in the GPIO user's guide - SPRUGV1.

Thanks and best regards,

Anthony

  • 0
    TI__Mastermind 42545 points

    Hi Anthony,

    KeyStone I and II do not multiplex many of the pins as is common with other TI processors. Most of the pins have a dedicated function. There are a group of pins, including GPIO, CORESEL[3:0] and TIMI[1:0], which are used for boot configuration. These pins must be driven or pulled to a discrete level when RESETFULL is released to define the boot mode of the part. Once the boot mode is latched these pins may be used for their primary function. In addition GPIO[31:17] are shared with the EMU[33:19] emulation trace connections. EMU connections have very strict routing rules. It would require special buffering and routing if you plan on connecting the trace interface to your JTAG interface. Internally the GPIOs pins can be used as an interrupt source but this isn't considered a multiplex function. It's just a function of the GPIO block. 

    Regards, Bill

  • 0 in reply to Bill Taboada
    TI__Mastermind 30110 points

    Thanks a lot Bill:)