Greetings,
If I am not using Sync-Ethernet / IEEE1588, can I leave TSREFCLKN and TSREFCLKP as NC?
Thanks,
Justin
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Greetings,
If I am not using Sync-Ethernet / IEEE1588, can I leave TSREFCLKN and TSREFCLKP as NC?
Thanks,
Justin
Justin,
These are differential clock inputs. You should follwo the guidance in the Hardware Design Guide SPRABI2. The P input should be pulled to CVDD through a 1K ohm resistor. The N input should go to ground.
Tom
Hi Tom,
Can you double check your information about the TSREFCLK? I was able to see in Keystone II Source Clock Input Requirements Application Note – Rev. 1.21 that what it says about this clock if unused is different than what you stated in your reply.
Justin
Justin,
You are correct. The 1K ohm resistor needs to be pulled to DVDD18 to support proper sequencing.
Tom
Hi Tom
I have query on placement of 1K resistor. As per 3.3 Unused Clock Inputs of SPRABI2C document it should be pulled down to GND. Can you have a look into it?
In addition to this I have one more question. Can we provide differential clock of 122.88MHz to TSREFCLK even if I am not using IEEE1588 interface?
Thanks,
Sachin
Sachin,
This post has mixed the requirements for an LVDS clock input (TSREFCLK) with an LJCB clock input (such as SYSCLK). The allowed solutions for unused clock inputs are different. Figure 3.3 in the KeyStone Hardware Design Guide SPRABI2C is for an LJCB clock input. The recommendation is connecting the P-input to CVDD and the N-input to GND through a 1K resistor. The recommendation for connecting the LVDS clock input TSREFCLK which operates on DVDD18 is to connect the P-input to DVDD18 through a 1K resistor and the N-input to GND through a 1K resistor. We are working to get a KeyStone-II Hardware Design guide published which will clarify these recommendations.
Tom
Tom,
As per table 13 and figure 13 of SPRABI2C document, even clocks RP1CLK and RP1FB are LVDS clocks they have recommended to connect P terminal directly to DVDD1V8 and N terminal to GND through 1K resistor.
Sachin
Sachin,
I see you found an inconsistency in our recommendations. Going forward, we intend to keep the single resistor solution for the LJCB and the dual resistor solution for the LVDS inputs due to the high supply voltage. There will be new versions of the KeyStone-I and KeyStone-II Hardware Design Guides released later this month with these corrections.
Tom