I have a custom design based on the DaVinci DM6446 running GHS Integrity RTOS. The USB controller is configured as a USB host and the only device connected to it is a USB WiFi dongle based on the RT3572 chipset.
The problem I am having is sometimes the data I read from the FIFO2 (which I am using for BULK IN transfers) intermittenty contains data errors. I have a USB analyzer and have been able to determine that the data in error is always the first 8 bytes read from the FIFO. These 8 bytes are the same 8 bytes I wrote to the FIFO0 in the last setup transfer. The USB analyzer captured both packets and shows the correct data on the bus for both transfers. But, it's as if the data I transmitted out via FIFO0 was received in FIFO2, overwriting the first 8 bytes of the actual BULK IN data. Referring to the image below, when the BULK IN data shown at index 2527704 was read from the FIFO, the full packet of data matched that captured by the analyzer except the first 8 bytes matched those shown in the SETUP transfer captured by the analyzer at index 2527708.
Originally, my driver was accessing all FIFO2 using PIO. I have modified it to use DMA for reading FIFO2 keeping all other FIFO transfers as PIO. The results are the same.
Can anyone help me determine potential causes of this behavior?
