• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 99 subscribers
  • Views 402 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

USB Host stops working when DVFS takes place on OMAP L138EVM Board.

Mughees Chohan
Intellectual 530 points
Other Parts Discussed in Thread: OMAPL138, OMAP-L138

Hi All,

I am working on USB Host Driver for omapl138 platform from Logic PD. I have implemented a host driver and it works flawlessly. BUT when CPU freq changes the driver stops working. The moment DVFS takes place the session bit clears and VBUS drops to zero. Dont know what is goin on here. I have tried different bypass sources, Phy modes but no success. But if I set the session bit again the driver starts to work but it does not happen every time. Can anybody suggest what is going on.

Regards,

Mughees

  • 0
    TI__Guru* 81335 points

    Hi Mughees,

    Thanks for the post.

    Mughees: said:

     I have implemented a host driver and it works flawlessly.

    For which platform, you have implemented the USB Host driver? Is it application/design specific?

    The USB Host driver are available in OMAP-L138 Starterware Version 01.10.03.03.

    http://processors.wiki.ti.com/index.php/StarterWare

    Linux USB Driver: Please refer the musb drivers from linux source (linux-##.##.##.##/drivers/usb/musb).

  • 0 in reply to Raja
    Intellectual 530 points

    Hi Rajasekaran K,

    I have implemented for our proprietary RTOS. However I am having SOC(I guess) related problems when I switch clocks for DVFS on Omap l138. Thanks

    Regards,

  • 0 in reply to Mughees Chohan
    TI__Guru**** 177476 points

    Mughees

    What is your targeted CPU frequency? When you change the CPU frequency, did you change the output divider as well? Can you send us your PLL configuration register value before and after the change?

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Intellectual 530 points

    Hi David,

    Thanks for the reply. I am using Mentor USB 2.0 core of omapl138. I switch from CPU Frequency of 576Mhz to 432Mhz. The divider values are in the following order:

    FREQ:   /* multiplier, div1, div2, div3, div4, div5, div6, div7, pre, post */    (div1 and dv2 control sysclk1 and sysclk2 respectively)

    576: {0x18, 0x0, 0x1, 0x11, 0x3, 0x2, 0x0, 0x5, 0x0, 0x1, 0x0, 0x1}

    432: {0x12, 0x0, 0x1, 0x11, 0x3, 0x2, 0x0, 0x5, 0x0, 0x1, 0x0, 0x1}

    So to change the frequency I change the multiplier only since we should  keep the ratio of USB0 CLK(Sysclk2) to Sysclk1 fixed that is sysclk1 should be twice of sysclk2 as mentioned in the omapl138 documentation. These dividers are the values I program in the Divider registers. I have verified that these values are written correctly. This change gives a glitch or something I am not sure, which in turn either causes the VBUS to drop and session bit to clear(less frequent) or causes connection and disconnection interrupts of the USB keeping VBUS the same (more frequent) and hence USB drive attached stops running. I have worked on many TI platforms with this IP (DM8148,am335x) but dont get this issue. Thanks.

    Regards,

    Mughees Ahmed Chohan

  • 0 in reply to Mughees Chohan
    Intellectual 530 points

    David,

    I have also tried different Reference clocks for the pll (the square one and the oscin one), differnet EXTSRCCLK for Bypass and disabled usb module before and after DVFS through power domain but no success. Maybe you can suggest a safer way of clock switching that can make the usb module immune to these changes. Also the USB2.0 subsystem requires a reference clock for its internal PLL. I have configured this reference clock to be sourced from AUXCLK in my case since REFCLKIN is not available for my configuration. Thanks.

    Regards,

    Mughees

  • 0 in reply to Mughees Chohan
    Intellectual 530 points

    Hi David,

    Finally got it working. The issue was with the Bypass clock of PLL0. I set it to PLL1_SYSCLK3 and it works now. I think I was not setting it properly before. I think it would be a good thing if we document this if it is not already been done. Thanks a lot it works. Thanks.

    Regards,

    Mughees Ahmed Chohan