AM335x GPMC direction pin

Vishy Canadam

Hi,

I am using the pinmux utility to set up my GPMC pins. I chose the GPMC addresses GPMC_A[15:0] in the MODE 1 column and data pins GPMC_AD[15:0] in MODE 0 column. When I select the GPMC DIR pin in MODE 4 column, I get a IO set violation.

I am using a buffer on the data bus and I need to use the GPMC_DIR pin for buffer read/write control.

Please let me know how to solve this IO set violation.

Thx

Vishy

over 12 years ago

0 MaciejKucia over 12 years ago

Mastermind 7925 points

This might help: http://processors.wiki.ti.com/index.php/Pin_Mux_Utility_for_ARM_MPU_Processors_v2#IO_Set_Violation_Status

Regards,
Maciej

0 Vishy Canadam over 12 years ago in reply to MaciejKucia

Prodigy 140 points

Hi Maciej,

Thx for the reply.

I had already seen that. It only explains what IO set violation means.

I still need an answer for how to get the GPMC DIR pin from AM335x.

Thx

Vishy

0 peaves over 12 years ago in reply to Vishy Canadam

TI__Guru 63105 points

There are 9 valid IO Sets that can be used to access the GPMC_DIR signal. They are IO Sets 4, 9, 14, 19, 24, 29, 34, 39, and 44.

You most select one of these IO Sets when using GPMC_DIR.

You may need to select one of these valid combinations of GPMC pin multiplexing before assigning other peripherals.

Regards,
Paul

0 Vishy Canadam over 12 years ago in reply to peaves

Prodigy 140 points

Paul,

Thx.

I figured out how to apply the sets in the pinmux utility and now I can resolve conflicts.

I used IO-set 19, unselected the unused higher order address bits, so I can use them as MMC0 interface and GPIOs.

Please confirm that is ok to do.

Thx

Vishy

Processors

Processors forum

AM335x GPMC direction pin