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About c6678 boot &the cache settings

David Yang1
Intellectual 435 points

Hi,Ti guys

I am using c6678 evm to test spi boot, and find out that our Bios program with 4k L1D cache cannt be booted properly, as in the bootroom code the cache is set to 32k. I am sure is the cache problem, for when I use not boot mode and set the Cache settings in gel to L1D4K cache, the program can be download and all core run to main(), and if I use 32K L1d cache gel, 1~7 corepac won't able to find main(). The same promble is discribed as solved in another post in e2e, only the guy was using no boot mode with gel to deal with the cache size.

Anyway, is there any way to set the cache in each core of c6678 during spi boot to 4k before ipc interrupt wakes 1~7 core up? I mean and code in core 0, or and measure before bootcode rom wake up core 0 like gel does in noboot mode?

Thank u

                                                                                                                                                                                               David Yang

  • 0
    TI__Genius 9065 points

    ROM bootloader will reserve some area to boot the application code. Your application code's memory map can not overlap with those, or boot might fail. In this case, if bootloader is reserving the L1D as whole cache. You need to load your code to somewhere else. When your application code runs, you can reconfiugre the L1D cache to your desire.