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DDR3 ECC setting method

KAZUHITO KONDO
Intellectual 285 points

Hello,

C6678 has DDR3 memory which is 2Gbyte and 36 bit including 4 bit ECC.
Could you tell me how to use ECCADDRx register? I consider as below.

It becomes the following default map.

  8000_0000 ~   FFFF_FFFF  -> Logical 32bit address (2GB)
8_0000_0000 ~ 8_7FFF_FFFF  -> Physical 36bit address

Then I think upper physical address in binary.

   8    0    0    0    0
1000_0000_0000_0000_0000
...*_****_****_****_***.

   8    7    F    F    F
1000_0111_1111_1111_1111
...*_****_****_****_***.

After that, I extract '*' indicated bit. ([32-17] of 33-bit address for ECC)

ECC_STRT_ADDR_1: 0x0000
ECC_END_ADDR1: 0x3FFF

Regards

  • 0
    TI__Expert 6815 points

    Hi,

    Here are the guidelines to program the ECC address range registers.

    1. Consider the 36-bit address you have programmed the XMC or MSMC_SES MPAX to map the DDR address to. By default, the MPAX will map first 2GB of DDR space starting at 0x8000_0000 to 36-bit physical address 0x8:0000_0000. You might have a different mapping in your application, so care must be taken to ensure your own MPAX mapping output is used.

    2. The mapping of course is linear, meaning 0x9000_0000 maps to physical address 0x8:1000_0000, 0xA000_0000 maps to 0x8:2000_0000 and so on.

    3. The lower 33 bits [32:0] of the 36b physical address are used by the DDR controller. Of these, the bits [32:17] should be used to program ECCADDR1/2 registers.

    4. Example, consider default mapping: Programming ECCCTL to 0xC0000003 will enable ECC calc for ADDR1 and ADDR2. Programming ECCADDR1 = 0x08000000 and ECCADDR2 = 0x18001000 will setup address ranges 0x8000_0000 to 0x9001_FFFF and 0xA000_0000 to 0xB001FFFF as ECC address space.

    Please let me know if you have any questions.

  • 0 in reply to Aditya
    Intellectual 285 points

    Hello Aditya

    Thank you for your advice. As my understanding, the ECCADDR2 value of your case is 0x18001000 (Not 0x18000100). Is it correct?

    When should I also execute following processing? Is it before PHY reset, after PHY reset or,,?

    ECCADDR1 = 0x08000000;
    ECCADDR2 = 0x18001000;
    ECCCTL = 0xC0000003;

    Regards

  • 0 in reply to KAZUHITO KONDO
    TI__Expert 6815 points

    Sorry, you are right. It is 0x18001000, not 0x18000100.


    You should execute those steps after PHY reset but before you write to SDCFG.

  • 0 in reply to Aditya
    Expert 2125 points

    Hi,

     Our customized board has C6678 with DDR3, capacity 1GB - width of 64bit. We have separate  DDR3 chip for ECC process.

    =========================

    Process 1 :  Disable ECC Option

    ==========================

    If I Disable ECC option and try to read/write the memory its working fine.. Memory fill is working fine

    =========================

    Process 2 :  Enable  ECC Option

    ==========================

    We have configured the registers for ECC as bellow:

    ECCADDR1 = 0x08000000;
    ECCADDR2 = 0x18001000;
    ECCCTL = 0xC0000003;

    When we try to read/write memory with sample data its not happening

    Is there any other registers I need to enable for ECC to happen ??

    Please suggest

  • 0 in reply to Avinash Neethi1
    TI__Expert 6815 points

    Hi Avinash,

    How are you reading/writing to memory with ECC enabled - through the CCS memory window, using the CPU or something else?

    A couple of things to keep in mind when using ECC:

    1. After initializing the DDR, all memory space configured as ECC should be filled with some known data before it is used for functional reads/writes.

    2. The reads/writes to ECC mapped space should always be 64-bit aligned and multiples of 64-bit.