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About c6678 srio priority

David Yang1
Intellectual 435 points

Hi, Ti guys,

I am using c6678 ccs5.1 to test srio on my own board. The srio module is configured to 1*1*1*1 mode with 5Ghz speed. And due to the massive income data from all the 4 port and the relatively low ddr rate on our board, we get wrong data on the receiving dsp. I am wondering if I can manually set higher priority to one of the 4 port, say the port connected with fpga, to ensure the reliablitity&validity of most essential data?

Thank you!

                                                                                                                                                                                                  David Yang

  • 0
    TI__Genius 13235 points

    Hi Yang,

     Thanks for posting to the forum. I had a couple of questions to gain more insight into your issue:

    •  Are you using direct I/O or message passing in your application?
    • Can you explain the application you are designing in more detail?
      • What devices are communicating over SRIO?
      • Are these devices all on one board or across several boards?

     Some comments based on the information you provided:

     Note: The following information is referenced from the KeyStone Architecture Serial Rapid IO (SRIO) User Guide (http://www.ti.com/lit/pdf/sprugw1)

    David Yang1 said:
    The srio module is configured to 1*1*1*1 mode with 5Ghz speed.

    You mentioned that you are using the 4 SRIO ports in 1x mode. It should be noted that the effective data bandwidth per differential pair on each port is 4 Gbps, due to the 8b/10b encoding scheme used. See section 1.1.3 Physical Layer 1x/4x LP-Serial Specification of the SRIO user guide.

    David Yang1 said:
    I am wondering if I can manually set higher priority to one of the 4 port, say the port connected with fpga, to ensure the reliablitity&validity of most essential data?

    Taking a data centric view of what is being transmitted over SRIO, the priority and CRF fields are used to set message priority during transmission. See section 2.3.2 Direct I/O Operation and section 2.3.3 Message Passing for further information on usage of the priority and CRF bits in SRIO messages.

    Please let us know if you have any other questions or concerns.

    Thanks,

    Clinton

  • 0 in reply to Clinton Rodgers
    Intellectual 435 points

    Hi, Clinton

    Thanks for your quick responding!

    About the details

    1,We are using direct IO, the source code is the Keystone_srio programme downloaded from the forum

    2,our target dsp is connected with 1 fpga, using two of the four ports, and with another 2 dsps, with 1 port each,all of them on 1 board. The fpga serves as data source.

    I am full aware of the 4Gbps maximum speed, and I understand there is a priority of 0~3 in the direct IO mode, the thing bothering me is that is this priority regarding to one port only(apply only within a port),or all the 4 ports? Say I set the priority of one port to 1, the other remain 0, when all port are operating, does my setting give an edge to the port with higher prio?

    Another question is that in direct IO mode, is all the 4port using the same TXU&RXU?

    Thanks,

    David Yang

     

  • 0 in reply to David Yang1
    TI__Genius 13235 points

    Hi David,

    Thanks for the additional information. Here is some feedback:

    David Yang1 said:
    the thing bothering me is that is this priority regarding to one port only(apply only within a port),or all the 4 ports? Say I set the priority of one port to 1, the other remain 0, when all port are operating, does my setting give an edge to the port with higher prio?

    You are correct, the packet priority is related to the transmit operation on a port-by-port basis (see 2.3.2.2 TX Operation in the SRIO User Guide). Based on your question, it sounds like you are interested in providing each port a priority level on your receiving device. This is not possible.

    From the view point of the RX packets, no prioritization is considered by the physical layer buffers at the ports. Subsequently, the shared buffers use a round robin approach to pull data from all 4 ports.

    An explanation can be found here: http://processors.wiki.ti.com/index.php/SRIO_Implementation_Facts#Inbound_and_Outbound_buffering

    David Yang1 said:
    Another question is that in direct IO mode, is all the 4port using the same TXU&RXU?

    The TXU and RXU are used in message passing mode. They are not used in direct IO mode.

    David Yang1 said:
    due to the massive income data from all the 4 port and the relatively low ddr rate on our board, we get wrong data on the receiving dsp.

    Going back to your original problem, do you have any way to buffer the data on the  FPGA or slow it down? Is this something that your application can tolerate?

    Thanks,

    Clinton

  • 0 in reply to Clinton Rodgers
    Intellectual 435 points

    Hi, Clinton

    Thanks for your quick reply!

    I think I have some idea with the outline now, I will check with our fpga guys about this problem.

    David Yang